2 files changed, 0 insertions, 170 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
index 6284f2f9..4d249524 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_api.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -17,143 +17,6 @@
 #include <nvgpu/flcnif_cmn.h>
 #include "pmuif/gpmuif_pg_rppg.h"
-/*---------------------------------------------------------*/
-/*perfmon task defines*/
-enum pmu_perfmon_cmd_start_fields {
-        COUNTER_ALLOC
-};
-enum {
-        PMU_PERFMON_CMD_ID_START = 0,
-        PMU_PERFMON_CMD_ID_STOP  = 1,
-        PMU_PERFMON_CMD_ID_INIT  = 2
-};
-struct pmu_perfmon_cmd_start_v3 {
-        u8 cmd_type;
-        u8 group_id;
-        u8 state_id;
-        u8 flags;
-        struct pmu_allocation_v3 counter_alloc;
-};
-struct pmu_perfmon_cmd_start_v2 {
-        u8 cmd_type;
-        u8 group_id;
-        u8 state_id;
-        u8 flags;
-        struct pmu_allocation_v2 counter_alloc;
-};
-struct pmu_perfmon_cmd_start_v1 {
-        u8 cmd_type;
-        u8 group_id;
-        u8 state_id;
-        u8 flags;
-        struct pmu_allocation_v1 counter_alloc;
-};
-struct pmu_perfmon_cmd_start_v0 {
-        u8 cmd_type;
-        u8 group_id;
-        u8 state_id;
-        u8 flags;
-        struct pmu_allocation_v0 counter_alloc;
-};
-struct pmu_perfmon_cmd_stop {
-        u8 cmd_type;
-};
-struct pmu_perfmon_cmd_init_v3 {
-        u8 cmd_type;
-        u8 to_decrease_count;
-        u8 base_counter_id;
-        u32 sample_period_us;
-        struct pmu_allocation_v3 counter_alloc;
-        u8 num_counters;
-        u8 samples_in_moving_avg;
-        u16 sample_buffer;
-};
-struct pmu_perfmon_cmd_init_v2 {
-        u8 cmd_type;
-        u8 to_decrease_count;
-        u8 base_counter_id;
-        u32 sample_period_us;
-        struct pmu_allocation_v2 counter_alloc;
-        u8 num_counters;
-        u8 samples_in_moving_avg;
-        u16 sample_buffer;
-};
-struct pmu_perfmon_cmd_init_v1 {
-        u8 cmd_type;
-        u8 to_decrease_count;
-        u8 base_counter_id;
-        u32 sample_period_us;
-        struct pmu_allocation_v1 counter_alloc;
-        u8 num_counters;
-        u8 samples_in_moving_avg;
-        u16 sample_buffer;
-};
-struct pmu_perfmon_cmd_init_v0 {
-        u8 cmd_type;
-        u8 to_decrease_count;
-        u8 base_counter_id;
-        u32 sample_period_us;
-        struct pmu_allocation_v0 counter_alloc;
-        u8 num_counters;
-        u8 samples_in_moving_avg;
-        u16 sample_buffer;
-};
-struct pmu_perfmon_cmd {
-        union {
-                u8 cmd_type;
-                struct pmu_perfmon_cmd_start_v0 start_v0;
-                struct pmu_perfmon_cmd_start_v1 start_v1;
-                struct pmu_perfmon_cmd_start_v2 start_v2;
-                struct pmu_perfmon_cmd_start_v3 start_v3;
-                struct pmu_perfmon_cmd_stop stop;
-                struct pmu_perfmon_cmd_init_v0 init_v0;
-                struct pmu_perfmon_cmd_init_v1 init_v1;
-                struct pmu_perfmon_cmd_init_v2 init_v2;
-                struct pmu_perfmon_cmd_init_v3 init_v3;
-        };
-};
-struct pmu_zbc_cmd {
-        u8 cmd_type;
-        u8 pad;
-        u16 entry_mask;
-};
-/* PERFMON MSG */
-enum {
-        PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
-        PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
-        PMU_PERFMON_MSG_ID_INIT_EVENT     = 2,
-        PMU_PERFMON_MSG_ID_ACK            = 3
-};
-struct pmu_perfmon_msg_generic {
-        u8 msg_type;
-        u8 state_id;
-        u8 group_id;
-        u8 data;
-};
-struct pmu_perfmon_msg {
-        union {
-                u8 msg_type;
-                struct pmu_perfmon_msg_generic gen;
-        };
-};
-/*---------------------------------------------------------*/
 /* ACR Commands/Message structures */
 enum {
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index b4a69720..87246f42 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -134,39 +134,6 @@ struct pmu_ucode_desc_v1 {
 */
 #define ACR_ERROR_INVALID_TRANSCFG_SETUP        (0xAC120001)
-/* PERFMON */
-#define PMU_DOMAIN_GROUP_PSTATE         0
-#define PMU_DOMAIN_GROUP_GPC2CLK        1
-#define PMU_DOMAIN_GROUP_NUM            2
-/* TBD: smart strategy */
-#define PMU_PERFMON_PCT_TO_INC          58
-#define PMU_PERFMON_PCT_TO_DEC          23
-struct pmu_perfmon_counter_v0 {
-        u8 index;
-        u8 flags;
-        u8 group_id;
-        u8 valid;
-        u16 upper_threshold; /* units of 0.01% */
-        u16 lower_threshold; /* units of 0.01% */
-};
-struct pmu_perfmon_counter_v2 {
-        u8 index;
-        u8 flags;
-        u8 group_id;
-        u8 valid;
-        u16 upper_threshold; /* units of 0.01% */
-        u16 lower_threshold; /* units of 0.01% */
-        u32 scale;
-};
-#define PMU_PERFMON_FLAG_ENABLE_INCREASE        (0x00000001)
-#define PMU_PERFMON_FLAG_ENABLE_DECREASE        (0x00000002)
-#define PMU_PERFMON_FLAG_CLEAR_PREV             (0x00000004)
 #define PMU_PGENG_GR_BUFFER_IDX_INIT    (0)
 #define PMU_PGENG_GR_BUFFER_IDX_ZBC     (1)
 #define PMU_PGENG_GR_BUFFER_IDX_FECS    (2)

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index 6284f2f9..4d249524 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -17,143 +17,6 @@
17	#include <nvgpu/flcnif_cmn.h>	17	#include <nvgpu/flcnif_cmn.h>
18	#include "pmuif/gpmuif_pg_rppg.h"	18	#include "pmuif/gpmuif_pg_rppg.h"
19		19
20	/---------------------------------------------------------/
21
22	/perfmon task defines/
23	enum pmu_perfmon_cmd_start_fields {
24	COUNTER_ALLOC
25	};
26
27	enum {
28	PMU_PERFMON_CMD_ID_START = 0,
29	PMU_PERFMON_CMD_ID_STOP = 1,
30	PMU_PERFMON_CMD_ID_INIT = 2
31	};
32
33	struct pmu_perfmon_cmd_start_v3 {
34	u8 cmd_type;
35	u8 group_id;
36	u8 state_id;
37	u8 flags;
38	struct pmu_allocation_v3 counter_alloc;
39	};
40
41	struct pmu_perfmon_cmd_start_v2 {
42	u8 cmd_type;
43	u8 group_id;
44	u8 state_id;
45	u8 flags;
46	struct pmu_allocation_v2 counter_alloc;
47	};
48
49	struct pmu_perfmon_cmd_start_v1 {
50	u8 cmd_type;
51	u8 group_id;
52	u8 state_id;
53	u8 flags;
54	struct pmu_allocation_v1 counter_alloc;
55	};
56
57	struct pmu_perfmon_cmd_start_v0 {
58	u8 cmd_type;
59	u8 group_id;
60	u8 state_id;
61	u8 flags;
62	struct pmu_allocation_v0 counter_alloc;
63	};
64
65	struct pmu_perfmon_cmd_stop {
66	u8 cmd_type;
67	};
68
69	struct pmu_perfmon_cmd_init_v3 {
70	u8 cmd_type;
71	u8 to_decrease_count;
72	u8 base_counter_id;
73	u32 sample_period_us;
74	struct pmu_allocation_v3 counter_alloc;
75	u8 num_counters;
76	u8 samples_in_moving_avg;
77	u16 sample_buffer;
78	};
79
80	struct pmu_perfmon_cmd_init_v2 {
81	u8 cmd_type;
82	u8 to_decrease_count;
83	u8 base_counter_id;
84	u32 sample_period_us;
85	struct pmu_allocation_v2 counter_alloc;
86	u8 num_counters;
87	u8 samples_in_moving_avg;
88	u16 sample_buffer;
89	};
90
91	struct pmu_perfmon_cmd_init_v1 {
92	u8 cmd_type;
93	u8 to_decrease_count;
94	u8 base_counter_id;
95	u32 sample_period_us;
96	struct pmu_allocation_v1 counter_alloc;
97	u8 num_counters;
98	u8 samples_in_moving_avg;
99	u16 sample_buffer;
100	};
101
102	struct pmu_perfmon_cmd_init_v0 {
103	u8 cmd_type;
104	u8 to_decrease_count;
105	u8 base_counter_id;
106	u32 sample_period_us;
107	struct pmu_allocation_v0 counter_alloc;
108	u8 num_counters;
109	u8 samples_in_moving_avg;
110	u16 sample_buffer;
111	};
112
113	struct pmu_perfmon_cmd {
114	union {
115	u8 cmd_type;
116	struct pmu_perfmon_cmd_start_v0 start_v0;
117	struct pmu_perfmon_cmd_start_v1 start_v1;
118	struct pmu_perfmon_cmd_start_v2 start_v2;
119	struct pmu_perfmon_cmd_start_v3 start_v3;
120	struct pmu_perfmon_cmd_stop stop;
121	struct pmu_perfmon_cmd_init_v0 init_v0;
122	struct pmu_perfmon_cmd_init_v1 init_v1;
123	struct pmu_perfmon_cmd_init_v2 init_v2;
124	struct pmu_perfmon_cmd_init_v3 init_v3;
125	};
126	};
127
128	struct pmu_zbc_cmd {
129	u8 cmd_type;
130	u8 pad;
131	u16 entry_mask;
132	};
133
134	/* PERFMON MSG */
135	enum {
136	PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
137	PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
138	PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
139	PMU_PERFMON_MSG_ID_ACK = 3
140	};
141
142	struct pmu_perfmon_msg_generic {
143	u8 msg_type;
144	u8 state_id;
145	u8 group_id;
146	u8 data;
147	};
148
149	struct pmu_perfmon_msg {
150	union {
151	u8 msg_type;
152	struct pmu_perfmon_msg_generic gen;
153	};
154	};
155
156	/---------------------------------------------------------/
157	/* ACR Commands/Message structures */	20	/* ACR Commands/Message structures */
158		21
159	enum {	22	enum {


diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index b4a69720..87246f42 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -134,39 +134,6 @@ struct pmu_ucode_desc_v1 {
134	*/	134	*/
135	#define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001)	135	#define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001)
136		136
137	/* PERFMON */
138	#define PMU_DOMAIN_GROUP_PSTATE 0
139	#define PMU_DOMAIN_GROUP_GPC2CLK 1
140	#define PMU_DOMAIN_GROUP_NUM 2
141
142	/* TBD: smart strategy */
143	#define PMU_PERFMON_PCT_TO_INC 58
144	#define PMU_PERFMON_PCT_TO_DEC 23
145
146	struct pmu_perfmon_counter_v0 {
147	u8 index;
148	u8 flags;
149	u8 group_id;
150	u8 valid;
151	u16 upper_threshold; /* units of 0.01% */
152	u16 lower_threshold; /* units of 0.01% */
153	};
154
155	struct pmu_perfmon_counter_v2 {
156	u8 index;
157	u8 flags;
158	u8 group_id;
159	u8 valid;
160	u16 upper_threshold; /* units of 0.01% */
161	u16 lower_threshold; /* units of 0.01% */
162	u32 scale;
163	};
164
165	#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
166	#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
167	#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
168
169
170	#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)	137	#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)
171	#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)	138	#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
172	#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)	139	#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)