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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h6
-rw-r--r--drivers/gpu/nvgpu/gk20a/pramin_gk20a.c73
-rw-r--r--drivers/gpu/nvgpu/gk20a/pramin_gk20a.h36
3 files changed, 3 insertions, 112 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 2d304cff..f6b0b362 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -925,9 +925,6 @@ struct gpu_ops {
925 struct gr_ctx_buffer_desc *desc, 925 struct gr_ctx_buffer_desc *desc,
926 size_t size); 926 size_t size);
927 struct { 927 struct {
928 u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem,
929 struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl,
930 u32 w);
931 void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, 928 void (*exit)(struct gk20a *g, struct nvgpu_mem *mem,
932 struct nvgpu_sgl *sgl); 929 struct nvgpu_sgl *sgl);
933 u32 (*data032_r)(u32 i); 930 u32 (*data032_r)(u32 i);
@@ -1128,6 +1125,9 @@ struct gpu_ops {
1128 u32 source_id, u32 count, 1125 u32 source_id, u32 count,
1129 struct nvgpu_cpu_time_correlation_sample *); 1126 struct nvgpu_cpu_time_correlation_sample *);
1130 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); 1127 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
1128 u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem,
1129 struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl,
1130 u32 w);
1131 } bus; 1131 } bus;
1132 1132
1133 struct { 1133 struct {
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
deleted file mode 100644
index 8dde61a2..00000000
--- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/page_allocator.h>
24#include <nvgpu/bug.h>
25
26#include "gk20a/gk20a.h"
27#include "gk20a/mm_gk20a.h"
28#include "gk20a/pramin_gk20a.h"
29
30#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
31#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
32
33/* WARNING: returns pramin_window_lock taken, complement with pramin_exit() */
34u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
35 struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w)
36{
37 u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl);
38 u64 addr = bufbase + w * sizeof(u32);
39 u32 hi = (u32)((addr & ~(u64)0xfffff)
40 >> bus_bar0_window_target_bar0_window_base_shift_v());
41 u32 lo = (u32)(addr & 0xfffff);
42 u32 win = nvgpu_aperture_mask(g, mem,
43 bus_bar0_window_target_sys_mem_noncoherent_f(),
44 bus_bar0_window_target_sys_mem_coherent_f(),
45 bus_bar0_window_target_vid_mem_f()) |
46 bus_bar0_window_base_f(hi);
47
48 nvgpu_log(g, gpu_dbg_mem,
49 "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)",
50 hi, lo, mem, sgl, bufbase,
51 bufbase + nvgpu_sgt_get_phys(g, sgt, sgl),
52 nvgpu_sgt_get_length(sgt, sgl));
53
54 WARN_ON(!bufbase);
55
56 nvgpu_spinlock_acquire(&g->mm.pramin_window_lock);
57
58 if (g->mm.pramin_window != win) {
59 gk20a_writel(g, bus_bar0_window_r(), win);
60 gk20a_readl(g, bus_bar0_window_r());
61 g->mm.pramin_window = win;
62 }
63
64 return lo;
65}
66
67void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem,
68 struct nvgpu_sgl *sgl)
69{
70 nvgpu_log(g, gpu_dbg_mem, "end for %p,%p", mem, sgl);
71
72 nvgpu_spinlock_release(&g->mm.pramin_window_lock);
73}
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h
deleted file mode 100644
index a0a28088..00000000
--- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __PRAMIN_GK20A_H__
24#define __PRAMIN_GK20A_H__
25
26struct gk20a;
27struct nvgpu_mem;
28struct nvgpu_mem_sgl;
29
30u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
31 struct nvgpu_sgt *sgt,
32 struct nvgpu_sgl *sgl,
33 u32 w);
34void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem,
35 struct nvgpu_sgl *sgl);
36#endif