diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 15 |
2 files changed, 29 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index ff87edc2..c61b47c5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1040,6 +1040,21 @@ int gk20a_pm_finalize_poweron(struct device *dev) | |||
1040 | if (g->irq_stall != g->irq_nonstall) | 1040 | if (g->irq_stall != g->irq_nonstall) |
1041 | enable_irq(g->irq_nonstall); | 1041 | enable_irq(g->irq_nonstall); |
1042 | 1042 | ||
1043 | if (g->ops.xve.available_speeds) { | ||
1044 | u32 speed; | ||
1045 | |||
1046 | g->ops.xve.sw_init(dev); | ||
1047 | g->ops.xve.available_speeds(g, &speed); | ||
1048 | |||
1049 | /* Set to max speed */ | ||
1050 | speed = 1 << (fls(speed) - 1); | ||
1051 | err = g->ops.xve.set_speed(g, speed); | ||
1052 | if (err) { | ||
1053 | gk20a_err(dev, "Failed to set PCIe bus speed!\n"); | ||
1054 | goto done; | ||
1055 | } | ||
1056 | } | ||
1057 | |||
1043 | done: | 1058 | done: |
1044 | return err; | 1059 | return err; |
1045 | } | 1060 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d51fdea1..75b96f42 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -703,6 +703,14 @@ struct gpu_ops { | |||
703 | struct gk20a_cs_snapshot_client *client); | 703 | struct gk20a_cs_snapshot_client *client); |
704 | } css; | 704 | } css; |
705 | #endif | 705 | #endif |
706 | struct { | ||
707 | int (*sw_init)(struct device *dev); | ||
708 | int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); | ||
709 | int (*set_speed)(struct gk20a *g, u32 xve_link_speed); | ||
710 | void (*available_speeds)(struct gk20a *g, u32 *speed_mask); | ||
711 | u32 (*xve_readl)(struct gk20a *g, u32 reg); | ||
712 | void (*xve_writel)(struct gk20a *g, u32 reg, u32 val); | ||
713 | } xve; | ||
706 | }; | 714 | }; |
707 | 715 | ||
708 | struct nvgpu_bios_ucode { | 716 | struct nvgpu_bios_ucode { |
@@ -818,7 +826,7 @@ struct gk20a { | |||
818 | struct dentry *debugfs_timeslice_medium_priority_us; | 826 | struct dentry *debugfs_timeslice_medium_priority_us; |
819 | struct dentry *debugfs_timeslice_high_priority_us; | 827 | struct dentry *debugfs_timeslice_high_priority_us; |
820 | struct dentry *debugfs_runlist_interleave; | 828 | struct dentry *debugfs_runlist_interleave; |
821 | 829 | struct dentry *debugfs_xve; | |
822 | #endif | 830 | #endif |
823 | struct gk20a_ctxsw_ucode_info ctxsw_ucode_info; | 831 | struct gk20a_ctxsw_ucode_info ctxsw_ucode_info; |
824 | 832 | ||
@@ -937,6 +945,10 @@ struct gk20a { | |||
937 | u16 pci_subsystem_vendor_id, pci_subsystem_device_id; | 945 | u16 pci_subsystem_vendor_id, pci_subsystem_device_id; |
938 | u16 pci_class; | 946 | u16 pci_class; |
939 | u8 pci_revision; | 947 | u8 pci_revision; |
948 | |||
949 | /* PCIe power states. */ | ||
950 | bool xve_l0s; | ||
951 | bool xve_l1; | ||
940 | }; | 952 | }; |
941 | 953 | ||
942 | static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) | 954 | static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) |
@@ -1011,6 +1023,7 @@ enum gk20a_dbg_categories { | |||
1011 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ | 1023 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ |
1012 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ | 1024 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ |
1013 | gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */ | 1025 | gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */ |
1026 | gpu_dbg_xv = BIT(18), /* XVE debugging */ | ||
1014 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ | 1027 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ |
1015 | }; | 1028 | }; |
1016 | 1029 | ||