diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
21 files changed, 166 insertions, 165 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index d161a29c..dd96df16 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -130,7 +130,7 @@ int gk20a_read_ptimer(struct gk20a *g, u64 *value) | |||
130 | return -EBUSY; | 130 | return -EBUSY; |
131 | } | 131 | } |
132 | 132 | ||
133 | static int gk20a_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst) | 133 | static int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) |
134 | { | 134 | { |
135 | u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst); | 135 | u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst); |
136 | u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a()); | 136 | u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a()); |
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.h b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h index 01526f06..b2f8f8c9 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h | |||
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | struct gk20a; | 19 | struct gk20a; |
20 | struct gpu_ops; | 20 | struct gpu_ops; |
21 | struct mem_desc; | 21 | struct nvgpu_mem; |
22 | 22 | ||
23 | void gk20a_init_bus(struct gpu_ops *gops); | 23 | void gk20a_init_bus(struct gpu_ops *gops); |
24 | 24 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c index 926e21ef..0db6c21a 100644 --- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c | |||
@@ -52,7 +52,7 @@ static void gk20a_deinit_cde_img(struct gk20a_cde_ctx *cde_ctx) | |||
52 | unsigned int i; | 52 | unsigned int i; |
53 | 53 | ||
54 | for (i = 0; i < cde_ctx->num_bufs; i++) { | 54 | for (i = 0; i < cde_ctx->num_bufs; i++) { |
55 | struct mem_desc *mem = cde_ctx->mem + i; | 55 | struct nvgpu_mem *mem = cde_ctx->mem + i; |
56 | gk20a_gmmu_unmap_free(cde_ctx->vm, mem); | 56 | gk20a_gmmu_unmap_free(cde_ctx->vm, mem); |
57 | } | 57 | } |
58 | 58 | ||
@@ -226,7 +226,7 @@ static int gk20a_init_cde_buf(struct gk20a_cde_ctx *cde_ctx, | |||
226 | const struct firmware *img, | 226 | const struct firmware *img, |
227 | struct gk20a_cde_hdr_buf *buf) | 227 | struct gk20a_cde_hdr_buf *buf) |
228 | { | 228 | { |
229 | struct mem_desc *mem; | 229 | struct nvgpu_mem *mem; |
230 | int err; | 230 | int err; |
231 | 231 | ||
232 | /* check that the file can hold the buf */ | 232 | /* check that the file can hold the buf */ |
@@ -312,8 +312,8 @@ static int gk20a_init_cde_replace(struct gk20a_cde_ctx *cde_ctx, | |||
312 | const struct firmware *img, | 312 | const struct firmware *img, |
313 | struct gk20a_cde_hdr_replace *replace) | 313 | struct gk20a_cde_hdr_replace *replace) |
314 | { | 314 | { |
315 | struct mem_desc *source_mem; | 315 | struct nvgpu_mem *source_mem; |
316 | struct mem_desc *target_mem; | 316 | struct nvgpu_mem *target_mem; |
317 | u32 *target_mem_ptr; | 317 | u32 *target_mem_ptr; |
318 | u64 vaddr; | 318 | u64 vaddr; |
319 | int err; | 319 | int err; |
@@ -362,7 +362,7 @@ static int gk20a_init_cde_replace(struct gk20a_cde_ctx *cde_ctx, | |||
362 | static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx) | 362 | static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx) |
363 | { | 363 | { |
364 | struct gk20a *g = cde_ctx->g; | 364 | struct gk20a *g = cde_ctx->g; |
365 | struct mem_desc *target_mem; | 365 | struct nvgpu_mem *target_mem; |
366 | u32 *target_mem_ptr; | 366 | u32 *target_mem_ptr; |
367 | u64 new_data; | 367 | u64 new_data; |
368 | int user_id = 0, err; | 368 | int user_id = 0, err; |
@@ -451,7 +451,7 @@ static int gk20a_init_cde_param(struct gk20a_cde_ctx *cde_ctx, | |||
451 | const struct firmware *img, | 451 | const struct firmware *img, |
452 | struct gk20a_cde_hdr_param *param) | 452 | struct gk20a_cde_hdr_param *param) |
453 | { | 453 | { |
454 | struct mem_desc *target_mem; | 454 | struct nvgpu_mem *target_mem; |
455 | 455 | ||
456 | if (param->target_buf >= cde_ctx->num_bufs) { | 456 | if (param->target_buf >= cde_ctx->num_bufs) { |
457 | gk20a_warn(cde_ctx->dev, "cde: invalid buffer parameter. param idx = %d, target_buf=%u, num_bufs=%u", | 457 | gk20a_warn(cde_ctx->dev, "cde: invalid buffer parameter. param idx = %d, target_buf=%u, num_bufs=%u", |
@@ -545,7 +545,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx, | |||
545 | 545 | ||
546 | gpfifo_elem = *gpfifo; | 546 | gpfifo_elem = *gpfifo; |
547 | for (i = 0; i < num_elems; i++, cmd_elem++, gpfifo_elem++) { | 547 | for (i = 0; i < num_elems; i++, cmd_elem++, gpfifo_elem++) { |
548 | struct mem_desc *target_mem; | 548 | struct nvgpu_mem *target_mem; |
549 | 549 | ||
550 | /* validate the current entry */ | 550 | /* validate the current entry */ |
551 | if (cmd_elem->target_buf >= cde_ctx->num_bufs) { | 551 | if (cmd_elem->target_buf >= cde_ctx->num_bufs) { |
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h index a36f2401..ffd55b4d 100644 --- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h | |||
@@ -222,7 +222,7 @@ struct gk20a_cde_ctx { | |||
222 | struct vm_gk20a *vm; | 222 | struct vm_gk20a *vm; |
223 | 223 | ||
224 | /* buf converter configuration */ | 224 | /* buf converter configuration */ |
225 | struct mem_desc mem[MAX_CDE_BUFS]; | 225 | struct nvgpu_mem mem[MAX_CDE_BUFS]; |
226 | unsigned int num_bufs; | 226 | unsigned int num_bufs; |
227 | 227 | ||
228 | /* buffer patching params (where should patching be done) */ | 228 | /* buffer patching params (where should patching be done) */ |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 7a4e4861..ac0bae32 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -110,7 +110,7 @@ struct gk20a_gpu_ctx { | |||
110 | struct vm_gk20a *vm; | 110 | struct vm_gk20a *vm; |
111 | 111 | ||
112 | /* cmd buf mem_desc */ | 112 | /* cmd buf mem_desc */ |
113 | struct mem_desc cmd_buf_mem; | 113 | struct nvgpu_mem cmd_buf_mem; |
114 | 114 | ||
115 | struct nvgpu_list_node list; | 115 | struct nvgpu_list_node list; |
116 | 116 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index e13a903f..d0e2be79 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -2117,7 +2117,7 @@ static void gk20a_submit_append_priv_cmdbuf(struct channel_gk20a *c, | |||
2117 | struct priv_cmd_entry *cmd) | 2117 | struct priv_cmd_entry *cmd) |
2118 | { | 2118 | { |
2119 | struct gk20a *g = c->g; | 2119 | struct gk20a *g = c->g; |
2120 | struct mem_desc *gpfifo_mem = &c->gpfifo.mem; | 2120 | struct nvgpu_mem *gpfifo_mem = &c->gpfifo.mem; |
2121 | struct nvgpu_gpfifo x = { | 2121 | struct nvgpu_gpfifo x = { |
2122 | .entry0 = u64_lo32(cmd->gva), | 2122 | .entry0 = u64_lo32(cmd->gva), |
2123 | .entry1 = u64_hi32(cmd->gva) | | 2123 | .entry1 = u64_hi32(cmd->gva) | |
@@ -2148,7 +2148,7 @@ static int gk20a_submit_append_gpfifo(struct channel_gk20a *c, | |||
2148 | u32 len = num_entries * sizeof(struct nvgpu_gpfifo); | 2148 | u32 len = num_entries * sizeof(struct nvgpu_gpfifo); |
2149 | u32 start = c->gpfifo.put * sizeof(struct nvgpu_gpfifo); | 2149 | u32 start = c->gpfifo.put * sizeof(struct nvgpu_gpfifo); |
2150 | u32 end = start + len; /* exclusive */ | 2150 | u32 end = start + len; /* exclusive */ |
2151 | struct mem_desc *gpfifo_mem = &c->gpfifo.mem; | 2151 | struct nvgpu_mem *gpfifo_mem = &c->gpfifo.mem; |
2152 | struct nvgpu_gpfifo *cpu_src; | 2152 | struct nvgpu_gpfifo *cpu_src; |
2153 | int err; | 2153 | int err; |
2154 | 2154 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index d6356652..8c863124 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -193,7 +193,7 @@ struct channel_gk20a { | |||
193 | 193 | ||
194 | struct channel_ctx_gk20a ch_ctx; | 194 | struct channel_ctx_gk20a ch_ctx; |
195 | 195 | ||
196 | struct mem_desc inst_block; | 196 | struct nvgpu_mem inst_block; |
197 | 197 | ||
198 | u64 userd_iova; | 198 | u64 userd_iova; |
199 | u64 userd_gpu_va; | 199 | u64 userd_gpu_va; |
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h index d6cea7c6..a95eaeae 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.h | |||
@@ -114,7 +114,7 @@ gk20a_cs_snapshot_client_from_list(struct nvgpu_list_node *node) | |||
114 | struct gk20a_cs_snapshot { | 114 | struct gk20a_cs_snapshot { |
115 | unsigned long perfmon_ids[PM_BITMAP_SIZE]; | 115 | unsigned long perfmon_ids[PM_BITMAP_SIZE]; |
116 | struct nvgpu_list_node clients; | 116 | struct nvgpu_list_node clients; |
117 | struct mem_desc hw_memdesc; | 117 | struct nvgpu_mem hw_memdesc; |
118 | /* pointer to allocated cpu_va memory where GPU place data */ | 118 | /* pointer to allocated cpu_va memory where GPU place data */ |
119 | struct gk20a_cs_snapshot_fifo_entry *hw_snapshot; | 119 | struct gk20a_cs_snapshot_fifo_entry *hw_snapshot; |
120 | struct gk20a_cs_snapshot_fifo_entry *hw_end; | 120 | struct gk20a_cs_snapshot_fifo_entry *hw_end; |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index 2e0809ee..b3c52852 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -95,7 +95,7 @@ static void gk20a_fb_set_debug_mode(struct gk20a *g, bool enable) | |||
95 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | 95 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); |
96 | } | 96 | } |
97 | 97 | ||
98 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb) | 98 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) |
99 | { | 99 | { |
100 | struct nvgpu_timeout timeout; | 100 | struct nvgpu_timeout timeout; |
101 | u32 addr_lo; | 101 | u32 addr_lo; |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h index a808ba6d..f9f4fbd0 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h | |||
@@ -15,11 +15,11 @@ | |||
15 | #define FB_GK20A_H | 15 | #define FB_GK20A_H |
16 | 16 | ||
17 | struct gk20a; | 17 | struct gk20a; |
18 | struct mem_desc; | 18 | struct nvgpu_mem; |
19 | 19 | ||
20 | void gk20a_init_fb(struct gpu_ops *gops); | 20 | void gk20a_init_fb(struct gpu_ops *gops); |
21 | void fb_gk20a_reset(struct gk20a *g); | 21 | void fb_gk20a_reset(struct gk20a *g); |
22 | void gk20a_fb_init_hw(struct gk20a *g); | 22 | void gk20a_fb_init_hw(struct gk20a *g); |
23 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb); | 23 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); |
24 | 24 | ||
25 | #endif | 25 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index b4e3bad1..3ed28718 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -60,7 +60,7 @@ struct gk20a_fecs_trace_hash_ent { | |||
60 | 60 | ||
61 | struct gk20a_fecs_trace { | 61 | struct gk20a_fecs_trace { |
62 | 62 | ||
63 | struct mem_desc trace_buf; | 63 | struct nvgpu_mem trace_buf; |
64 | DECLARE_HASHTABLE(pid_hash_table, GK20A_FECS_TRACE_HASH_BITS); | 64 | DECLARE_HASHTABLE(pid_hash_table, GK20A_FECS_TRACE_HASH_BITS); |
65 | struct nvgpu_mutex hash_lock; | 65 | struct nvgpu_mutex hash_lock; |
66 | struct nvgpu_mutex poll_lock; | 66 | struct nvgpu_mutex poll_lock; |
@@ -620,7 +620,7 @@ static int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
620 | phys_addr_t pa; | 620 | phys_addr_t pa; |
621 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | 621 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; |
622 | struct gk20a_fecs_trace *trace = g->fecs_trace; | 622 | struct gk20a_fecs_trace *trace = g->fecs_trace; |
623 | struct mem_desc *mem = &ch_ctx->gr_ctx->mem; | 623 | struct nvgpu_mem *mem = &ch_ctx->gr_ctx->mem; |
624 | u32 context_ptr = gk20a_fecs_trace_fecs_context_ptr(ch); | 624 | u32 context_ptr = gk20a_fecs_trace_fecs_context_ptr(ch); |
625 | pid_t pid; | 625 | pid_t pid; |
626 | u32 aperture; | 626 | u32 aperture; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b8b0c9b0..1e9a8e15 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3963,7 +3963,7 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | |||
3963 | u32 flags) | 3963 | u32 flags) |
3964 | { | 3964 | { |
3965 | struct gk20a *g = c->g; | 3965 | struct gk20a *g = c->g; |
3966 | struct mem_desc *mem = &c->inst_block; | 3966 | struct nvgpu_mem *mem = &c->inst_block; |
3967 | 3967 | ||
3968 | gk20a_dbg_fn(""); | 3968 | gk20a_dbg_fn(""); |
3969 | 3969 | ||
@@ -4097,7 +4097,7 @@ int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority) | |||
4097 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) | 4097 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) |
4098 | { | 4098 | { |
4099 | struct gk20a *g = c->g; | 4099 | struct gk20a *g = c->g; |
4100 | struct mem_desc *mem = &c->inst_block; | 4100 | struct nvgpu_mem *mem = &c->inst_block; |
4101 | 4101 | ||
4102 | gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->hw_chid); | 4102 | gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->hw_chid); |
4103 | 4103 | ||
@@ -4109,7 +4109,7 @@ void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) | |||
4109 | int gk20a_fifo_setup_userd(struct channel_gk20a *c) | 4109 | int gk20a_fifo_setup_userd(struct channel_gk20a *c) |
4110 | { | 4110 | { |
4111 | struct gk20a *g = c->g; | 4111 | struct gk20a *g = c->g; |
4112 | struct mem_desc *mem = &g->fifo.userd; | 4112 | struct nvgpu_mem *mem = &g->fifo.userd; |
4113 | u32 offset = c->hw_chid * g->fifo.userd_entry_size / sizeof(u32); | 4113 | u32 offset = c->hw_chid * g->fifo.userd_entry_size / sizeof(u32); |
4114 | 4114 | ||
4115 | gk20a_dbg_fn(""); | 4115 | gk20a_dbg_fn(""); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 6d1b902e..d5456ea1 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -63,7 +63,7 @@ struct fifo_runlist_info_gk20a { | |||
63 | unsigned long *active_channels; | 63 | unsigned long *active_channels; |
64 | unsigned long *active_tsgs; | 64 | unsigned long *active_tsgs; |
65 | /* Each engine has its own SW and HW runlist buffer.*/ | 65 | /* Each engine has its own SW and HW runlist buffer.*/ |
66 | struct mem_desc mem[MAX_RUNLIST_BUFFERS]; | 66 | struct nvgpu_mem mem[MAX_RUNLIST_BUFFERS]; |
67 | u32 cur_buffer; | 67 | u32 cur_buffer; |
68 | u32 total_entries; | 68 | u32 total_entries; |
69 | u32 pbdma_bitmask; /* pbdmas supported for this runlist*/ | 69 | u32 pbdma_bitmask; /* pbdmas supported for this runlist*/ |
@@ -166,7 +166,7 @@ struct fifo_gk20a { | |||
166 | struct nvgpu_mutex lock; | 166 | struct nvgpu_mutex lock; |
167 | } profile; | 167 | } profile; |
168 | #endif | 168 | #endif |
169 | struct mem_desc userd; | 169 | struct nvgpu_mem userd; |
170 | u32 userd_entry_size; | 170 | u32 userd_entry_size; |
171 | 171 | ||
172 | unsigned int used_channels; | 172 | unsigned int used_channels; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index db7b3c5d..4fa8b76f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -258,7 +258,7 @@ struct gpu_ops { | |||
258 | struct gr_ctx_desc *gr_ctx); | 258 | struct gr_ctx_desc *gr_ctx); |
259 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, | 259 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, |
260 | struct channel_ctx_gk20a *ch_ctx, | 260 | struct channel_ctx_gk20a *ch_ctx, |
261 | struct mem_desc *mem); | 261 | struct nvgpu_mem *mem); |
262 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, | 262 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, |
263 | struct channel_gk20a *c, | 263 | struct channel_gk20a *c, |
264 | bool enable); | 264 | bool enable); |
@@ -279,7 +279,7 @@ struct gpu_ops { | |||
279 | u32 expect_delay); | 279 | u32 expect_delay); |
280 | void (*init_cyclestats)(struct gk20a *g); | 280 | void (*init_cyclestats)(struct gk20a *g); |
281 | void (*enable_cde_in_fecs)(struct gk20a *g, | 281 | void (*enable_cde_in_fecs)(struct gk20a *g, |
282 | struct mem_desc *mem); | 282 | struct nvgpu_mem *mem); |
283 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, | 283 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, |
284 | u64 sms, bool enable); | 284 | u64 sms, bool enable); |
285 | void (*bpt_reg_info)(struct gk20a *g, | 285 | void (*bpt_reg_info)(struct gk20a *g, |
@@ -329,7 +329,7 @@ struct gpu_ops { | |||
329 | u32 compute_preempt_mode); | 329 | u32 compute_preempt_mode); |
330 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); | 330 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); |
331 | void (*update_boosted_ctx)(struct gk20a *g, | 331 | void (*update_boosted_ctx)(struct gk20a *g, |
332 | struct mem_desc *mem, | 332 | struct nvgpu_mem *mem, |
333 | struct gr_ctx_desc *gr_ctx); | 333 | struct gr_ctx_desc *gr_ctx); |
334 | int (*fuse_override)(struct gk20a *g); | 334 | int (*fuse_override)(struct gk20a *g); |
335 | void (*init_sm_id_table)(struct gk20a *g); | 335 | void (*init_sm_id_table)(struct gk20a *g); |
@@ -344,11 +344,11 @@ struct gpu_ops { | |||
344 | int (*commit_global_timeslice)(struct gk20a *g, | 344 | int (*commit_global_timeslice)(struct gk20a *g, |
345 | struct channel_gk20a *c, bool patch); | 345 | struct channel_gk20a *c, bool patch); |
346 | int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); | 346 | int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); |
347 | void (*restore_context_header)(struct gk20a *g, struct mem_desc *ctxheader); | 347 | void (*restore_context_header)(struct gk20a *g, struct nvgpu_mem *ctxheader); |
348 | void (*write_zcull_ptr)(struct gk20a *g, | 348 | void (*write_zcull_ptr)(struct gk20a *g, |
349 | struct mem_desc *mem, u64 gpu_va); | 349 | struct nvgpu_mem *mem, u64 gpu_va); |
350 | void (*write_pm_ptr)(struct gk20a *g, | 350 | void (*write_pm_ptr)(struct gk20a *g, |
351 | struct mem_desc *mem, u64 gpu_va); | 351 | struct nvgpu_mem *mem, u64 gpu_va); |
352 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); | 352 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); |
353 | void (*load_tpc_mask)(struct gk20a *g); | 353 | void (*load_tpc_mask)(struct gk20a *g); |
354 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); | 354 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); |
@@ -372,7 +372,7 @@ struct gpu_ops { | |||
372 | int (*vpr_info_fetch)(struct gk20a *g); | 372 | int (*vpr_info_fetch)(struct gk20a *g); |
373 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 373 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
374 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 374 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
375 | void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); | 375 | void (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); |
376 | void (*hub_isr)(struct gk20a *g); | 376 | void (*hub_isr)(struct gk20a *g); |
377 | } fb; | 377 | } fb; |
378 | struct { | 378 | struct { |
@@ -636,7 +636,7 @@ struct gpu_ops { | |||
636 | void (*l2_flush)(struct gk20a *g, bool invalidate); | 636 | void (*l2_flush)(struct gk20a *g, bool invalidate); |
637 | void (*cbc_clean)(struct gk20a *g); | 637 | void (*cbc_clean)(struct gk20a *g); |
638 | void (*set_big_page_size)(struct gk20a *g, | 638 | void (*set_big_page_size)(struct gk20a *g, |
639 | struct mem_desc *mem, int size); | 639 | struct nvgpu_mem *mem, int size); |
640 | u32 (*get_big_page_sizes)(void); | 640 | u32 (*get_big_page_sizes)(void); |
641 | u32 (*get_physical_addr_bits)(struct gk20a *g); | 641 | u32 (*get_physical_addr_bits)(struct gk20a *g); |
642 | int (*init_mm_setup_hw)(struct gk20a *g); | 642 | int (*init_mm_setup_hw)(struct gk20a *g); |
@@ -646,19 +646,19 @@ struct gpu_ops { | |||
646 | void (*remove_bar2_vm)(struct gk20a *g); | 646 | void (*remove_bar2_vm)(struct gk20a *g); |
647 | const struct gk20a_mmu_level * | 647 | const struct gk20a_mmu_level * |
648 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); | 648 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); |
649 | void (*init_pdb)(struct gk20a *g, struct mem_desc *inst_block, | 649 | void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block, |
650 | struct vm_gk20a *vm); | 650 | struct vm_gk20a *vm); |
651 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, | 651 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, |
652 | u32 flags); | 652 | u32 flags); |
653 | size_t (*get_vidmem_size)(struct gk20a *g); | 653 | size_t (*get_vidmem_size)(struct gk20a *g); |
654 | void (*init_inst_block)(struct mem_desc *inst_block, | 654 | void (*init_inst_block)(struct nvgpu_mem *inst_block, |
655 | struct vm_gk20a *vm, u32 big_page_size); | 655 | struct vm_gk20a *vm, u32 big_page_size); |
656 | bool (*mmu_fault_pending)(struct gk20a *g); | 656 | bool (*mmu_fault_pending)(struct gk20a *g); |
657 | } mm; | 657 | } mm; |
658 | struct { | 658 | struct { |
659 | u32 (*enter)(struct gk20a *g, struct mem_desc *mem, | 659 | u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, |
660 | struct page_alloc_chunk *chunk, u32 w); | 660 | struct page_alloc_chunk *chunk, u32 w); |
661 | void (*exit)(struct gk20a *g, struct mem_desc *mem, | 661 | void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, |
662 | struct page_alloc_chunk *chunk); | 662 | struct page_alloc_chunk *chunk); |
663 | u32 (*data032_r)(u32 i); | 663 | u32 (*data032_r)(u32 i); |
664 | } pramin; | 664 | } pramin; |
@@ -709,7 +709,7 @@ struct gpu_ops { | |||
709 | bool (*is_priv_load)(u32 falcon_id); | 709 | bool (*is_priv_load)(u32 falcon_id); |
710 | void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); | 710 | void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); |
711 | int (*alloc_blob_space)(struct gk20a *g, | 711 | int (*alloc_blob_space)(struct gk20a *g, |
712 | size_t size, struct mem_desc *mem); | 712 | size_t size, struct nvgpu_mem *mem); |
713 | int (*pmu_populate_loader_cfg)(struct gk20a *g, | 713 | int (*pmu_populate_loader_cfg)(struct gk20a *g, |
714 | void *lsfm, u32 *p_bl_gen_desc_size); | 714 | void *lsfm, u32 *p_bl_gen_desc_size); |
715 | int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, | 715 | int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, |
@@ -820,7 +820,7 @@ struct gpu_ops { | |||
820 | void (*init_hw)(struct gk20a *g); | 820 | void (*init_hw)(struct gk20a *g); |
821 | void (*isr)(struct gk20a *g); | 821 | void (*isr)(struct gk20a *g); |
822 | int (*read_ptimer)(struct gk20a *g, u64 *value); | 822 | int (*read_ptimer)(struct gk20a *g, u64 *value); |
823 | int (*bar1_bind)(struct gk20a *g, struct mem_desc *bar1_inst); | 823 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
824 | } bus; | 824 | } bus; |
825 | 825 | ||
826 | int (*bios_init)(struct gk20a *g); | 826 | int (*bios_init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 360b8c97..971e2320 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -699,7 +699,7 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, | |||
699 | } | 699 | } |
700 | } | 700 | } |
701 | 701 | ||
702 | static u32 fecs_current_ctx_data(struct gk20a *g, struct mem_desc *inst_block) | 702 | static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) |
703 | { | 703 | { |
704 | u32 ptr = u64_lo32(gk20a_mm_inst_block_addr(g, inst_block) | 704 | u32 ptr = u64_lo32(gk20a_mm_inst_block_addr(g, inst_block) |
705 | >> ram_in_base_shift_v()); | 705 | >> ram_in_base_shift_v()); |
@@ -741,7 +741,7 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, | |||
741 | } | 741 | } |
742 | 742 | ||
743 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, | 743 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, |
744 | struct mem_desc *mem, u64 gpu_va) | 744 | struct nvgpu_mem *mem, u64 gpu_va) |
745 | { | 745 | { |
746 | u32 va = u64_lo32(gpu_va >> 8); | 746 | u32 va = u64_lo32(gpu_va >> 8); |
747 | 747 | ||
@@ -750,7 +750,7 @@ void gr_gk20a_write_zcull_ptr(struct gk20a *g, | |||
750 | } | 750 | } |
751 | 751 | ||
752 | void gr_gk20a_write_pm_ptr(struct gk20a *g, | 752 | void gr_gk20a_write_pm_ptr(struct gk20a *g, |
753 | struct mem_desc *mem, u64 gpu_va) | 753 | struct nvgpu_mem *mem, u64 gpu_va) |
754 | { | 754 | { |
755 | u32 va = u64_lo32(gpu_va >> 8); | 755 | u32 va = u64_lo32(gpu_va >> 8); |
756 | 756 | ||
@@ -761,9 +761,9 @@ void gr_gk20a_write_pm_ptr(struct gk20a *g, | |||
761 | static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) | 761 | static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) |
762 | { | 762 | { |
763 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 763 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
764 | struct mem_desc *mem = &ch_ctx->gr_ctx->mem; | 764 | struct nvgpu_mem *mem = &ch_ctx->gr_ctx->mem; |
765 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 765 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
766 | struct mem_desc *ctxheader = &ctx->mem; | 766 | struct nvgpu_mem *ctxheader = &ctx->mem; |
767 | int ret = 0; | 767 | int ret = 0; |
768 | 768 | ||
769 | gk20a_dbg_fn(""); | 769 | gk20a_dbg_fn(""); |
@@ -1579,15 +1579,15 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1579 | u32 ctx_header_words; | 1579 | u32 ctx_header_words; |
1580 | u32 i; | 1580 | u32 i; |
1581 | u32 data; | 1581 | u32 data; |
1582 | struct mem_desc *gold_mem = &gr->global_ctx_buffer[GOLDEN_CTX].mem; | 1582 | struct nvgpu_mem *gold_mem = &gr->global_ctx_buffer[GOLDEN_CTX].mem; |
1583 | struct mem_desc *gr_mem = &ch_ctx->gr_ctx->mem; | 1583 | struct nvgpu_mem *gr_mem = &ch_ctx->gr_ctx->mem; |
1584 | u32 err = 0; | 1584 | u32 err = 0; |
1585 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 1585 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
1586 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 1586 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
1587 | u32 last_method_data = 0; | 1587 | u32 last_method_data = 0; |
1588 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 1588 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
1589 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 1589 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
1590 | struct mem_desc *ctxheader = &ctx->mem; | 1590 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1591 | 1591 | ||
1592 | gk20a_dbg_fn(""); | 1592 | gk20a_dbg_fn(""); |
1593 | 1593 | ||
@@ -1836,7 +1836,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1836 | bool enable_smpc_ctxsw) | 1836 | bool enable_smpc_ctxsw) |
1837 | { | 1837 | { |
1838 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 1838 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
1839 | struct mem_desc *mem; | 1839 | struct nvgpu_mem *mem; |
1840 | u32 data; | 1840 | u32 data; |
1841 | int ret; | 1841 | int ret; |
1842 | 1842 | ||
@@ -1893,11 +1893,11 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1893 | { | 1893 | { |
1894 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 1894 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
1895 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; | 1895 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; |
1896 | struct mem_desc *gr_mem; | 1896 | struct nvgpu_mem *gr_mem; |
1897 | u32 data; | 1897 | u32 data; |
1898 | u64 virt_addr; | 1898 | u64 virt_addr; |
1899 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 1899 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
1900 | struct mem_desc *ctxheader = &ctx->mem; | 1900 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1901 | int ret; | 1901 | int ret; |
1902 | 1902 | ||
1903 | gk20a_dbg_fn(""); | 1903 | gk20a_dbg_fn(""); |
@@ -2018,7 +2018,7 @@ cleanup_pm_buf: | |||
2018 | gk20a_gmmu_unmap(c->vm, pm_ctx->mem.gpu_va, pm_ctx->mem.size, | 2018 | gk20a_gmmu_unmap(c->vm, pm_ctx->mem.gpu_va, pm_ctx->mem.size, |
2019 | gk20a_mem_flag_none); | 2019 | gk20a_mem_flag_none); |
2020 | gk20a_gmmu_free(g, &pm_ctx->mem); | 2020 | gk20a_gmmu_free(g, &pm_ctx->mem); |
2021 | memset(&pm_ctx->mem, 0, sizeof(struct mem_desc)); | 2021 | memset(&pm_ctx->mem, 0, sizeof(struct nvgpu_mem)); |
2022 | 2022 | ||
2023 | gk20a_enable_channel_tsg(g, c); | 2023 | gk20a_enable_channel_tsg(g, c); |
2024 | return ret; | 2024 | return ret; |
@@ -2035,9 +2035,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
2035 | u64 virt_addr = 0; | 2035 | u64 virt_addr = 0; |
2036 | u32 v, data; | 2036 | u32 v, data; |
2037 | int ret = 0; | 2037 | int ret = 0; |
2038 | struct mem_desc *mem = &ch_ctx->gr_ctx->mem; | 2038 | struct nvgpu_mem *mem = &ch_ctx->gr_ctx->mem; |
2039 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 2039 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
2040 | struct mem_desc *ctxheader = &ctx->mem; | 2040 | struct nvgpu_mem *ctxheader = &ctx->mem; |
2041 | 2041 | ||
2042 | gk20a_dbg_fn(""); | 2042 | gk20a_dbg_fn(""); |
2043 | 2043 | ||
@@ -2249,7 +2249,7 @@ static void gr_gk20a_init_ctxsw_ucode_segments( | |||
2249 | 2249 | ||
2250 | static int gr_gk20a_copy_ctxsw_ucode_segments( | 2250 | static int gr_gk20a_copy_ctxsw_ucode_segments( |
2251 | struct gk20a *g, | 2251 | struct gk20a *g, |
2252 | struct mem_desc *dst, | 2252 | struct nvgpu_mem *dst, |
2253 | struct gk20a_ctxsw_ucode_segments *segments, | 2253 | struct gk20a_ctxsw_ucode_segments *segments, |
2254 | u32 *bootimage, | 2254 | u32 *bootimage, |
2255 | u32 *code, u32 *data) | 2255 | u32 *code, u32 *data) |
@@ -2826,7 +2826,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g, | |||
2826 | u64 *g_bfr_va = c->ch_ctx.global_ctx_buffer_va; | 2826 | u64 *g_bfr_va = c->ch_ctx.global_ctx_buffer_va; |
2827 | u64 *g_bfr_size = c->ch_ctx.global_ctx_buffer_size; | 2827 | u64 *g_bfr_size = c->ch_ctx.global_ctx_buffer_size; |
2828 | struct gr_gk20a *gr = &g->gr; | 2828 | struct gr_gk20a *gr = &g->gr; |
2829 | struct mem_desc *mem; | 2829 | struct nvgpu_mem *mem; |
2830 | u64 gpu_va; | 2830 | u64 gpu_va; |
2831 | u32 i; | 2831 | u32 i; |
2832 | gk20a_dbg_fn(""); | 2832 | gk20a_dbg_fn(""); |
@@ -5085,7 +5085,7 @@ out: | |||
5085 | static int gr_gk20a_init_access_map(struct gk20a *g) | 5085 | static int gr_gk20a_init_access_map(struct gk20a *g) |
5086 | { | 5086 | { |
5087 | struct gr_gk20a *gr = &g->gr; | 5087 | struct gr_gk20a *gr = &g->gr; |
5088 | struct mem_desc *mem = &gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem; | 5088 | struct nvgpu_mem *mem = &gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem; |
5089 | u32 w, nr_pages = | 5089 | u32 w, nr_pages = |
5090 | DIV_ROUND_UP(gr->ctx_vars.priv_access_map_size, | 5090 | DIV_ROUND_UP(gr->ctx_vars.priv_access_map_size, |
5091 | PAGE_SIZE); | 5091 | PAGE_SIZE); |
@@ -6645,7 +6645,7 @@ int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size) | |||
6645 | } | 6645 | } |
6646 | 6646 | ||
6647 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, | 6647 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, |
6648 | struct mem_desc *inst_block) | 6648 | struct nvgpu_mem *inst_block) |
6649 | { | 6649 | { |
6650 | u32 data = fecs_current_ctx_data(g, inst_block); | 6650 | u32 data = fecs_current_ctx_data(g, inst_block); |
6651 | 6651 | ||
@@ -7131,7 +7131,7 @@ static void gr_gk20a_init_sm_dsm_reg_info(void) | |||
7131 | static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, | 7131 | static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, |
7132 | struct channel_ctx_gk20a *ch_ctx, | 7132 | struct channel_ctx_gk20a *ch_ctx, |
7133 | u32 addr, u32 data, | 7133 | u32 addr, u32 data, |
7134 | struct mem_desc *mem) | 7134 | struct nvgpu_mem *mem) |
7135 | { | 7135 | { |
7136 | u32 num_gpc = g->gr.gpc_count; | 7136 | u32 num_gpc = g->gr.gpc_count; |
7137 | u32 num_tpc; | 7137 | u32 num_tpc; |
@@ -8258,7 +8258,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
8258 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | 8258 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; |
8259 | bool gr_ctx_ready = false; | 8259 | bool gr_ctx_ready = false; |
8260 | bool pm_ctx_ready = false; | 8260 | bool pm_ctx_ready = false; |
8261 | struct mem_desc *current_mem = NULL; | 8261 | struct nvgpu_mem *current_mem = NULL; |
8262 | bool ch_is_curr_ctx, restart_gr_ctxsw = false; | 8262 | bool ch_is_curr_ctx, restart_gr_ctxsw = false; |
8263 | u32 i, j, offset, v; | 8263 | u32 i, j, offset, v; |
8264 | struct gr_gk20a *gr = &g->gr; | 8264 | struct gr_gk20a *gr = &g->gr; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 3a4d5e04..e05eeb3d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -205,7 +205,7 @@ struct gr_gk20a_isr_data { | |||
205 | 205 | ||
206 | struct gr_ctx_buffer_desc { | 206 | struct gr_ctx_buffer_desc { |
207 | void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); | 207 | void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); |
208 | struct mem_desc mem; | 208 | struct nvgpu_mem mem; |
209 | void *priv; | 209 | void *priv; |
210 | }; | 210 | }; |
211 | 211 | ||
@@ -321,8 +321,8 @@ struct gr_gk20a { | |||
321 | 321 | ||
322 | struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF]; | 322 | struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF]; |
323 | 323 | ||
324 | struct mem_desc mmu_wr_mem; | 324 | struct nvgpu_mem mmu_wr_mem; |
325 | struct mem_desc mmu_rd_mem; | 325 | struct nvgpu_mem mmu_rd_mem; |
326 | 326 | ||
327 | u8 *map_tiles; | 327 | u8 *map_tiles; |
328 | u32 map_tile_count; | 328 | u32 map_tile_count; |
@@ -385,7 +385,7 @@ struct gr_gk20a { | |||
385 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); | 385 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); |
386 | 386 | ||
387 | struct gr_ctx_desc { | 387 | struct gr_ctx_desc { |
388 | struct mem_desc mem; | 388 | struct nvgpu_mem mem; |
389 | 389 | ||
390 | u32 graphics_preempt_mode; | 390 | u32 graphics_preempt_mode; |
391 | u32 compute_preempt_mode; | 391 | u32 compute_preempt_mode; |
@@ -399,7 +399,7 @@ struct gr_ctx_desc { | |||
399 | }; | 399 | }; |
400 | 400 | ||
401 | struct ctx_header_desc { | 401 | struct ctx_header_desc { |
402 | struct mem_desc mem; | 402 | struct nvgpu_mem mem; |
403 | }; | 403 | }; |
404 | 404 | ||
405 | struct gk20a_ctxsw_ucode_segment { | 405 | struct gk20a_ctxsw_ucode_segment { |
@@ -441,8 +441,8 @@ struct gk20a_ctxsw_ucode_segments { | |||
441 | 441 | ||
442 | struct gk20a_ctxsw_ucode_info { | 442 | struct gk20a_ctxsw_ucode_info { |
443 | u64 *p_va; | 443 | u64 *p_va; |
444 | struct mem_desc inst_blk_desc; | 444 | struct nvgpu_mem inst_blk_desc; |
445 | struct mem_desc surface_desc; | 445 | struct nvgpu_mem surface_desc; |
446 | struct gk20a_ctxsw_ucode_segments fecs; | 446 | struct gk20a_ctxsw_ucode_segments fecs; |
447 | struct gk20a_ctxsw_ucode_segments gpccs; | 447 | struct gk20a_ctxsw_ucode_segments gpccs; |
448 | }; | 448 | }; |
@@ -526,7 +526,7 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr); | |||
526 | /* pmu */ | 526 | /* pmu */ |
527 | int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); | 527 | int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); |
528 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, | 528 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, |
529 | struct mem_desc *inst_block); | 529 | struct nvgpu_mem *inst_block); |
530 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | 530 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); |
531 | 531 | ||
532 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | 532 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); |
@@ -717,10 +717,10 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g); | |||
717 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 717 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
718 | 718 | ||
719 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, | 719 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, |
720 | struct mem_desc *mem, u64 gpu_va); | 720 | struct nvgpu_mem *mem, u64 gpu_va); |
721 | 721 | ||
722 | void gr_gk20a_write_pm_ptr(struct gk20a *g, | 722 | void gr_gk20a_write_pm_ptr(struct gk20a *g, |
723 | struct mem_desc *mem, u64 gpu_va); | 723 | struct nvgpu_mem *mem, u64 gpu_va); |
724 | 724 | ||
725 | 725 | ||
726 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) | 726 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9c9fad1b..cdd0e541 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <nvgpu/timers.h> | 34 | #include <nvgpu/timers.h> |
35 | #include <nvgpu/pramin.h> | 35 | #include <nvgpu/pramin.h> |
36 | #include <nvgpu/list.h> | 36 | #include <nvgpu/list.h> |
37 | #include <nvgpu/mem_desc.h> | 37 | #include <nvgpu/nvgpu_mem.h> |
38 | #include <nvgpu/allocator.h> | 38 | #include <nvgpu/allocator.h> |
39 | #include <nvgpu/semaphore.h> | 39 | #include <nvgpu/semaphore.h> |
40 | #include <nvgpu/page_allocator.h> | 40 | #include <nvgpu/page_allocator.h> |
@@ -169,7 +169,7 @@ struct gk20a_dmabuf_priv { | |||
169 | 169 | ||
170 | struct gk20a_vidmem_buf { | 170 | struct gk20a_vidmem_buf { |
171 | struct gk20a *g; | 171 | struct gk20a *g; |
172 | struct mem_desc *mem; | 172 | struct nvgpu_mem *mem; |
173 | struct dma_buf *dmabuf; | 173 | struct dma_buf *dmabuf; |
174 | void *dmabuf_priv; | 174 | void *dmabuf_priv; |
175 | void (*dmabuf_priv_delete)(void *); | 175 | void (*dmabuf_priv_delete)(void *); |
@@ -457,7 +457,7 @@ static int gk20a_init_mm_reset_enable_hw(struct gk20a *g) | |||
457 | return 0; | 457 | return 0; |
458 | } | 458 | } |
459 | 459 | ||
460 | void gk20a_remove_vm(struct vm_gk20a *vm, struct mem_desc *inst_block) | 460 | void gk20a_remove_vm(struct vm_gk20a *vm, struct nvgpu_mem *inst_block) |
461 | { | 461 | { |
462 | struct gk20a *g = vm->mm->g; | 462 | struct gk20a *g = vm->mm->g; |
463 | 463 | ||
@@ -1866,7 +1866,7 @@ int gk20a_vidmem_buf_alloc(struct gk20a *g, size_t bytes) | |||
1866 | nvgpu_mutex_release(&g->mm.vidmem.first_clear_mutex); | 1866 | nvgpu_mutex_release(&g->mm.vidmem.first_clear_mutex); |
1867 | } | 1867 | } |
1868 | 1868 | ||
1869 | buf->mem = nvgpu_kzalloc(g, sizeof(struct mem_desc)); | 1869 | buf->mem = nvgpu_kzalloc(g, sizeof(struct nvgpu_mem)); |
1870 | if (!buf->mem) | 1870 | if (!buf->mem) |
1871 | goto err_kfree; | 1871 | goto err_kfree; |
1872 | 1872 | ||
@@ -1931,7 +1931,7 @@ int gk20a_vidbuf_access_memory(struct gk20a *g, struct dma_buf *dmabuf, | |||
1931 | { | 1931 | { |
1932 | #if defined(CONFIG_GK20A_VIDMEM) | 1932 | #if defined(CONFIG_GK20A_VIDMEM) |
1933 | struct gk20a_vidmem_buf *vidmem_buf; | 1933 | struct gk20a_vidmem_buf *vidmem_buf; |
1934 | struct mem_desc *mem; | 1934 | struct nvgpu_mem *mem; |
1935 | int err = 0; | 1935 | int err = 0; |
1936 | 1936 | ||
1937 | if (gk20a_dmabuf_aperture(g, dmabuf) != APERTURE_VIDMEM) | 1937 | if (gk20a_dmabuf_aperture(g, dmabuf) != APERTURE_VIDMEM) |
@@ -2519,13 +2519,13 @@ u64 gk20a_gmmu_fixed_map(struct vm_gk20a *vm, | |||
2519 | aperture); | 2519 | aperture); |
2520 | } | 2520 | } |
2521 | 2521 | ||
2522 | int gk20a_gmmu_alloc(struct gk20a *g, size_t size, struct mem_desc *mem) | 2522 | int gk20a_gmmu_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem) |
2523 | { | 2523 | { |
2524 | return gk20a_gmmu_alloc_flags(g, 0, size, mem); | 2524 | return gk20a_gmmu_alloc_flags(g, 0, size, mem); |
2525 | } | 2525 | } |
2526 | 2526 | ||
2527 | int gk20a_gmmu_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, | 2527 | int gk20a_gmmu_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, |
2528 | struct mem_desc *mem) | 2528 | struct nvgpu_mem *mem) |
2529 | { | 2529 | { |
2530 | if (g->mm.vidmem_is_vidmem) { | 2530 | if (g->mm.vidmem_is_vidmem) { |
2531 | /* | 2531 | /* |
@@ -2549,7 +2549,7 @@ int gk20a_gmmu_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, | |||
2549 | return gk20a_gmmu_alloc_flags_sys(g, flags, size, mem); | 2549 | return gk20a_gmmu_alloc_flags_sys(g, flags, size, mem); |
2550 | } | 2550 | } |
2551 | 2551 | ||
2552 | int gk20a_gmmu_alloc_sys(struct gk20a *g, size_t size, struct mem_desc *mem) | 2552 | int gk20a_gmmu_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem) |
2553 | { | 2553 | { |
2554 | return gk20a_gmmu_alloc_flags_sys(g, 0, size, mem); | 2554 | return gk20a_gmmu_alloc_flags_sys(g, 0, size, mem); |
2555 | } | 2555 | } |
@@ -2574,7 +2574,7 @@ static void gk20a_dma_flags_to_attrs(struct dma_attrs *attrs, | |||
2574 | } | 2574 | } |
2575 | 2575 | ||
2576 | int gk20a_gmmu_alloc_flags_sys(struct gk20a *g, unsigned long flags, | 2576 | int gk20a_gmmu_alloc_flags_sys(struct gk20a *g, unsigned long flags, |
2577 | size_t size, struct mem_desc *mem) | 2577 | size_t size, struct nvgpu_mem *mem) |
2578 | { | 2578 | { |
2579 | struct device *d = dev_from_gk20a(g); | 2579 | struct device *d = dev_from_gk20a(g); |
2580 | int err; | 2580 | int err; |
@@ -2631,7 +2631,7 @@ fail_free: | |||
2631 | return err; | 2631 | return err; |
2632 | } | 2632 | } |
2633 | 2633 | ||
2634 | static void gk20a_gmmu_free_sys(struct gk20a *g, struct mem_desc *mem) | 2634 | static void gk20a_gmmu_free_sys(struct gk20a *g, struct nvgpu_mem *mem) |
2635 | { | 2635 | { |
2636 | struct device *d = dev_from_gk20a(g); | 2636 | struct device *d = dev_from_gk20a(g); |
2637 | 2637 | ||
@@ -2666,7 +2666,7 @@ static void gk20a_gmmu_free_sys(struct gk20a *g, struct mem_desc *mem) | |||
2666 | } | 2666 | } |
2667 | 2667 | ||
2668 | #if defined(CONFIG_GK20A_VIDMEM) | 2668 | #if defined(CONFIG_GK20A_VIDMEM) |
2669 | static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct mem_desc *mem) | 2669 | static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct nvgpu_mem *mem) |
2670 | { | 2670 | { |
2671 | struct gk20a_fence *gk20a_fence_out = NULL; | 2671 | struct gk20a_fence *gk20a_fence_out = NULL; |
2672 | struct gk20a_fence *gk20a_last_fence = NULL; | 2672 | struct gk20a_fence *gk20a_last_fence = NULL; |
@@ -2728,14 +2728,14 @@ static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct mem_desc *mem) | |||
2728 | } | 2728 | } |
2729 | #endif | 2729 | #endif |
2730 | 2730 | ||
2731 | int gk20a_gmmu_alloc_vid(struct gk20a *g, size_t size, struct mem_desc *mem) | 2731 | int gk20a_gmmu_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem) |
2732 | { | 2732 | { |
2733 | return gk20a_gmmu_alloc_flags_vid(g, | 2733 | return gk20a_gmmu_alloc_flags_vid(g, |
2734 | NVGPU_DMA_NO_KERNEL_MAPPING, size, mem); | 2734 | NVGPU_DMA_NO_KERNEL_MAPPING, size, mem); |
2735 | } | 2735 | } |
2736 | 2736 | ||
2737 | int gk20a_gmmu_alloc_flags_vid(struct gk20a *g, unsigned long flags, | 2737 | int gk20a_gmmu_alloc_flags_vid(struct gk20a *g, unsigned long flags, |
2738 | size_t size, struct mem_desc *mem) | 2738 | size_t size, struct nvgpu_mem *mem) |
2739 | { | 2739 | { |
2740 | return gk20a_gmmu_alloc_flags_vid_at(g, flags, size, mem, 0); | 2740 | return gk20a_gmmu_alloc_flags_vid_at(g, flags, size, mem, 0); |
2741 | } | 2741 | } |
@@ -2756,7 +2756,7 @@ static u64 __gk20a_gmmu_alloc(struct nvgpu_allocator *allocator, dma_addr_t at, | |||
2756 | #endif | 2756 | #endif |
2757 | 2757 | ||
2758 | int gk20a_gmmu_alloc_flags_vid_at(struct gk20a *g, unsigned long flags, | 2758 | int gk20a_gmmu_alloc_flags_vid_at(struct gk20a *g, unsigned long flags, |
2759 | size_t size, struct mem_desc *mem, dma_addr_t at) | 2759 | size_t size, struct nvgpu_mem *mem, dma_addr_t at) |
2760 | { | 2760 | { |
2761 | #if defined(CONFIG_GK20A_VIDMEM) | 2761 | #if defined(CONFIG_GK20A_VIDMEM) |
2762 | u64 addr; | 2762 | u64 addr; |
@@ -2831,7 +2831,7 @@ fail_physfree: | |||
2831 | #endif | 2831 | #endif |
2832 | } | 2832 | } |
2833 | 2833 | ||
2834 | static void gk20a_gmmu_free_vid(struct gk20a *g, struct mem_desc *mem) | 2834 | static void gk20a_gmmu_free_vid(struct gk20a *g, struct nvgpu_mem *mem) |
2835 | { | 2835 | { |
2836 | #if defined(CONFIG_GK20A_VIDMEM) | 2836 | #if defined(CONFIG_GK20A_VIDMEM) |
2837 | bool was_empty; | 2837 | bool was_empty; |
@@ -2863,7 +2863,7 @@ static void gk20a_gmmu_free_vid(struct gk20a *g, struct mem_desc *mem) | |||
2863 | #endif | 2863 | #endif |
2864 | } | 2864 | } |
2865 | 2865 | ||
2866 | void gk20a_gmmu_free(struct gk20a *g, struct mem_desc *mem) | 2866 | void gk20a_gmmu_free(struct gk20a *g, struct nvgpu_mem *mem) |
2867 | { | 2867 | { |
2868 | switch (mem->aperture) { | 2868 | switch (mem->aperture) { |
2869 | case APERTURE_SYSMEM: | 2869 | case APERTURE_SYSMEM: |
@@ -2879,7 +2879,7 @@ void gk20a_gmmu_free(struct gk20a *g, struct mem_desc *mem) | |||
2879 | * If mem is in VIDMEM, return base address in vidmem | 2879 | * If mem is in VIDMEM, return base address in vidmem |
2880 | * else return IOVA address for SYSMEM | 2880 | * else return IOVA address for SYSMEM |
2881 | */ | 2881 | */ |
2882 | u64 gk20a_mem_get_base_addr(struct gk20a *g, struct mem_desc *mem, | 2882 | u64 gk20a_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem, |
2883 | u32 flags) | 2883 | u32 flags) |
2884 | { | 2884 | { |
2885 | struct nvgpu_page_alloc *alloc; | 2885 | struct nvgpu_page_alloc *alloc; |
@@ -2900,14 +2900,14 @@ u64 gk20a_mem_get_base_addr(struct gk20a *g, struct mem_desc *mem, | |||
2900 | } | 2900 | } |
2901 | 2901 | ||
2902 | #if defined(CONFIG_GK20A_VIDMEM) | 2902 | #if defined(CONFIG_GK20A_VIDMEM) |
2903 | static struct mem_desc *get_pending_mem_desc(struct mm_gk20a *mm) | 2903 | static struct nvgpu_mem *get_pending_mem_desc(struct mm_gk20a *mm) |
2904 | { | 2904 | { |
2905 | struct mem_desc *mem = NULL; | 2905 | struct nvgpu_mem *mem = NULL; |
2906 | 2906 | ||
2907 | nvgpu_mutex_acquire(&mm->vidmem.clear_list_mutex); | 2907 | nvgpu_mutex_acquire(&mm->vidmem.clear_list_mutex); |
2908 | if (!nvgpu_list_empty(&mm->vidmem.clear_list_head)) { | 2908 | if (!nvgpu_list_empty(&mm->vidmem.clear_list_head)) { |
2909 | mem = nvgpu_list_first_entry(&mm->vidmem.clear_list_head, | 2909 | mem = nvgpu_list_first_entry(&mm->vidmem.clear_list_head, |
2910 | mem_desc, clear_list_entry); | 2910 | nvgpu_mem, clear_list_entry); |
2911 | nvgpu_list_del(&mem->clear_list_entry); | 2911 | nvgpu_list_del(&mem->clear_list_entry); |
2912 | } | 2912 | } |
2913 | nvgpu_mutex_release(&mm->vidmem.clear_list_mutex); | 2913 | nvgpu_mutex_release(&mm->vidmem.clear_list_mutex); |
@@ -2920,7 +2920,7 @@ static void gk20a_vidmem_clear_mem_worker(struct work_struct *work) | |||
2920 | struct mm_gk20a *mm = container_of(work, struct mm_gk20a, | 2920 | struct mm_gk20a *mm = container_of(work, struct mm_gk20a, |
2921 | vidmem.clear_mem_worker); | 2921 | vidmem.clear_mem_worker); |
2922 | struct gk20a *g = mm->g; | 2922 | struct gk20a *g = mm->g; |
2923 | struct mem_desc *mem; | 2923 | struct nvgpu_mem *mem; |
2924 | 2924 | ||
2925 | while ((mem = get_pending_mem_desc(mm)) != NULL) { | 2925 | while ((mem = get_pending_mem_desc(mm)) != NULL) { |
2926 | gk20a_gmmu_clear_vidmem_mem(g, mem); | 2926 | gk20a_gmmu_clear_vidmem_mem(g, mem); |
@@ -2939,13 +2939,13 @@ static void gk20a_vidmem_clear_mem_worker(struct work_struct *work) | |||
2939 | #endif | 2939 | #endif |
2940 | 2940 | ||
2941 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, size_t size, | 2941 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, size_t size, |
2942 | struct mem_desc *mem) | 2942 | struct nvgpu_mem *mem) |
2943 | { | 2943 | { |
2944 | return gk20a_gmmu_alloc_map_flags(vm, 0, size, mem); | 2944 | return gk20a_gmmu_alloc_map_flags(vm, 0, size, mem); |
2945 | } | 2945 | } |
2946 | 2946 | ||
2947 | int gk20a_gmmu_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, | 2947 | int gk20a_gmmu_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, |
2948 | size_t size, struct mem_desc *mem) | 2948 | size_t size, struct nvgpu_mem *mem) |
2949 | { | 2949 | { |
2950 | if (vm->mm->vidmem_is_vidmem) { | 2950 | if (vm->mm->vidmem_is_vidmem) { |
2951 | /* | 2951 | /* |
@@ -2970,13 +2970,13 @@ int gk20a_gmmu_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, | |||
2970 | } | 2970 | } |
2971 | 2971 | ||
2972 | int gk20a_gmmu_alloc_map_sys(struct vm_gk20a *vm, size_t size, | 2972 | int gk20a_gmmu_alloc_map_sys(struct vm_gk20a *vm, size_t size, |
2973 | struct mem_desc *mem) | 2973 | struct nvgpu_mem *mem) |
2974 | { | 2974 | { |
2975 | return gk20a_gmmu_alloc_map_flags_sys(vm, 0, size, mem); | 2975 | return gk20a_gmmu_alloc_map_flags_sys(vm, 0, size, mem); |
2976 | } | 2976 | } |
2977 | 2977 | ||
2978 | int gk20a_gmmu_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags, | 2978 | int gk20a_gmmu_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags, |
2979 | size_t size, struct mem_desc *mem) | 2979 | size_t size, struct nvgpu_mem *mem) |
2980 | { | 2980 | { |
2981 | int err = gk20a_gmmu_alloc_flags_sys(vm->mm->g, flags, size, mem); | 2981 | int err = gk20a_gmmu_alloc_flags_sys(vm->mm->g, flags, size, mem); |
2982 | 2982 | ||
@@ -2999,14 +2999,14 @@ fail_free: | |||
2999 | } | 2999 | } |
3000 | 3000 | ||
3001 | int gk20a_gmmu_alloc_map_vid(struct vm_gk20a *vm, size_t size, | 3001 | int gk20a_gmmu_alloc_map_vid(struct vm_gk20a *vm, size_t size, |
3002 | struct mem_desc *mem) | 3002 | struct nvgpu_mem *mem) |
3003 | { | 3003 | { |
3004 | return gk20a_gmmu_alloc_map_flags_vid(vm, | 3004 | return gk20a_gmmu_alloc_map_flags_vid(vm, |
3005 | NVGPU_DMA_NO_KERNEL_MAPPING, size, mem); | 3005 | NVGPU_DMA_NO_KERNEL_MAPPING, size, mem); |
3006 | } | 3006 | } |
3007 | 3007 | ||
3008 | int gk20a_gmmu_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags, | 3008 | int gk20a_gmmu_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags, |
3009 | size_t size, struct mem_desc *mem) | 3009 | size_t size, struct nvgpu_mem *mem) |
3010 | { | 3010 | { |
3011 | int err = gk20a_gmmu_alloc_flags_vid(vm->mm->g, flags, size, mem); | 3011 | int err = gk20a_gmmu_alloc_flags_vid(vm->mm->g, flags, size, mem); |
3012 | 3012 | ||
@@ -3028,7 +3028,7 @@ fail_free: | |||
3028 | return err; | 3028 | return err; |
3029 | } | 3029 | } |
3030 | 3030 | ||
3031 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct mem_desc *mem) | 3031 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem) |
3032 | { | 3032 | { |
3033 | if (mem->gpu_va) | 3033 | if (mem->gpu_va) |
3034 | gk20a_gmmu_unmap(vm, mem->gpu_va, mem->size, gk20a_mem_flag_none); | 3034 | gk20a_gmmu_unmap(vm, mem->gpu_va, mem->size, gk20a_mem_flag_none); |
@@ -4583,7 +4583,7 @@ void gk20a_deinit_vm(struct vm_gk20a *vm) | |||
4583 | gk20a_vm_free_entries(vm, &vm->pdb, 0); | 4583 | gk20a_vm_free_entries(vm, &vm->pdb, 0); |
4584 | } | 4584 | } |
4585 | 4585 | ||
4586 | int gk20a_alloc_inst_block(struct gk20a *g, struct mem_desc *inst_block) | 4586 | int gk20a_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block) |
4587 | { | 4587 | { |
4588 | struct device *dev = dev_from_gk20a(g); | 4588 | struct device *dev = dev_from_gk20a(g); |
4589 | int err; | 4589 | int err; |
@@ -4600,13 +4600,13 @@ int gk20a_alloc_inst_block(struct gk20a *g, struct mem_desc *inst_block) | |||
4600 | return 0; | 4600 | return 0; |
4601 | } | 4601 | } |
4602 | 4602 | ||
4603 | void gk20a_free_inst_block(struct gk20a *g, struct mem_desc *inst_block) | 4603 | void gk20a_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block) |
4604 | { | 4604 | { |
4605 | if (inst_block->size) | 4605 | if (inst_block->size) |
4606 | gk20a_gmmu_free(g, inst_block); | 4606 | gk20a_gmmu_free(g, inst_block); |
4607 | } | 4607 | } |
4608 | 4608 | ||
4609 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct mem_desc *inst_block) | 4609 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct nvgpu_mem *inst_block) |
4610 | { | 4610 | { |
4611 | u64 addr; | 4611 | u64 addr; |
4612 | if (g->mm.has_physical_mode) | 4612 | if (g->mm.has_physical_mode) |
@@ -4622,7 +4622,7 @@ static int gk20a_init_bar1_vm(struct mm_gk20a *mm) | |||
4622 | int err; | 4622 | int err; |
4623 | struct vm_gk20a *vm = &mm->bar1.vm; | 4623 | struct vm_gk20a *vm = &mm->bar1.vm; |
4624 | struct gk20a *g = gk20a_from_mm(mm); | 4624 | struct gk20a *g = gk20a_from_mm(mm); |
4625 | struct mem_desc *inst_block = &mm->bar1.inst_block; | 4625 | struct nvgpu_mem *inst_block = &mm->bar1.inst_block; |
4626 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; | 4626 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; |
4627 | 4627 | ||
4628 | mm->bar1.aperture_size = bar1_aperture_size_mb_gk20a() << 20; | 4628 | mm->bar1.aperture_size = bar1_aperture_size_mb_gk20a() << 20; |
@@ -4653,7 +4653,7 @@ static int gk20a_init_system_vm(struct mm_gk20a *mm) | |||
4653 | int err; | 4653 | int err; |
4654 | struct vm_gk20a *vm = &mm->pmu.vm; | 4654 | struct vm_gk20a *vm = &mm->pmu.vm; |
4655 | struct gk20a *g = gk20a_from_mm(mm); | 4655 | struct gk20a *g = gk20a_from_mm(mm); |
4656 | struct mem_desc *inst_block = &mm->pmu.inst_block; | 4656 | struct nvgpu_mem *inst_block = &mm->pmu.inst_block; |
4657 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; | 4657 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; |
4658 | u32 low_hole, aperture_size; | 4658 | u32 low_hole, aperture_size; |
4659 | 4659 | ||
@@ -4691,7 +4691,7 @@ static int gk20a_init_hwpm(struct mm_gk20a *mm) | |||
4691 | int err; | 4691 | int err; |
4692 | struct vm_gk20a *vm = &mm->pmu.vm; | 4692 | struct vm_gk20a *vm = &mm->pmu.vm; |
4693 | struct gk20a *g = gk20a_from_mm(mm); | 4693 | struct gk20a *g = gk20a_from_mm(mm); |
4694 | struct mem_desc *inst_block = &mm->hwpm.inst_block; | 4694 | struct nvgpu_mem *inst_block = &mm->hwpm.inst_block; |
4695 | 4695 | ||
4696 | err = gk20a_alloc_inst_block(g, inst_block); | 4696 | err = gk20a_alloc_inst_block(g, inst_block); |
4697 | if (err) | 4697 | if (err) |
@@ -4727,7 +4727,7 @@ static int gk20a_init_ce_vm(struct mm_gk20a *mm) | |||
4727 | false, false, "ce"); | 4727 | false, false, "ce"); |
4728 | } | 4728 | } |
4729 | 4729 | ||
4730 | void gk20a_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, | 4730 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
4731 | struct vm_gk20a *vm) | 4731 | struct vm_gk20a *vm) |
4732 | { | 4732 | { |
4733 | u64 pdb_addr = gk20a_mem_get_base_addr(g, &vm->pdb.mem, 0); | 4733 | u64 pdb_addr = gk20a_mem_get_base_addr(g, &vm->pdb.mem, 0); |
@@ -4747,7 +4747,7 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, | |||
4747 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); | 4747 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); |
4748 | } | 4748 | } |
4749 | 4749 | ||
4750 | void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, | 4750 | void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, |
4751 | u32 big_page_size) | 4751 | u32 big_page_size) |
4752 | { | 4752 | { |
4753 | struct gk20a *g = gk20a_from_vm(vm); | 4753 | struct gk20a *g = gk20a_from_vm(vm); |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 3c701907..db72ca79 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <asm/dma-iommu.h> | 24 | #include <asm/dma-iommu.h> |
25 | #include <asm/cacheflush.h> | 25 | #include <asm/cacheflush.h> |
26 | 26 | ||
27 | #include <nvgpu/mem_desc.h> | 27 | #include <nvgpu/nvgpu_mem.h> |
28 | #include <nvgpu/allocator.h> | 28 | #include <nvgpu/allocator.h> |
29 | #include <nvgpu/list.h> | 29 | #include <nvgpu/list.h> |
30 | #include <nvgpu/rbtree.h> | 30 | #include <nvgpu/rbtree.h> |
@@ -47,7 +47,7 @@ enum gk20a_mem_rw_flag { | |||
47 | }; | 47 | }; |
48 | 48 | ||
49 | struct gpfifo_desc { | 49 | struct gpfifo_desc { |
50 | struct mem_desc mem; | 50 | struct nvgpu_mem mem; |
51 | u32 entry_num; | 51 | u32 entry_num; |
52 | 52 | ||
53 | u32 get; | 53 | u32 get; |
@@ -61,7 +61,7 @@ struct gpfifo_desc { | |||
61 | }; | 61 | }; |
62 | 62 | ||
63 | struct patch_desc { | 63 | struct patch_desc { |
64 | struct mem_desc mem; | 64 | struct nvgpu_mem mem; |
65 | u32 data_count; | 65 | u32 data_count; |
66 | }; | 66 | }; |
67 | 67 | ||
@@ -72,14 +72,14 @@ struct zcull_ctx_desc { | |||
72 | }; | 72 | }; |
73 | 73 | ||
74 | struct pm_ctx_desc { | 74 | struct pm_ctx_desc { |
75 | struct mem_desc mem; | 75 | struct nvgpu_mem mem; |
76 | u32 pm_mode; | 76 | u32 pm_mode; |
77 | }; | 77 | }; |
78 | 78 | ||
79 | struct gk20a; | 79 | struct gk20a; |
80 | 80 | ||
81 | struct compbit_store_desc { | 81 | struct compbit_store_desc { |
82 | struct mem_desc mem; | 82 | struct nvgpu_mem mem; |
83 | 83 | ||
84 | /* The value that is written to the hardware. This depends on | 84 | /* The value that is written to the hardware. This depends on |
85 | * on the number of ltcs and is not an address. */ | 85 | * on the number of ltcs and is not an address. */ |
@@ -124,7 +124,7 @@ struct gk20a_comptags { | |||
124 | 124 | ||
125 | struct gk20a_mm_entry { | 125 | struct gk20a_mm_entry { |
126 | /* backing for */ | 126 | /* backing for */ |
127 | struct mem_desc mem; | 127 | struct nvgpu_mem mem; |
128 | u32 woffset; /* if >0, mem is a shadow copy, owned by another entry */ | 128 | u32 woffset; /* if >0, mem is a shadow copy, owned by another entry */ |
129 | int pgsz; | 129 | int pgsz; |
130 | struct gk20a_mm_entry *entries; | 130 | struct gk20a_mm_entry *entries; |
@@ -132,7 +132,7 @@ struct gk20a_mm_entry { | |||
132 | }; | 132 | }; |
133 | 133 | ||
134 | struct priv_cmd_queue { | 134 | struct priv_cmd_queue { |
135 | struct mem_desc mem; | 135 | struct nvgpu_mem mem; |
136 | u32 size; /* num of entries in words */ | 136 | u32 size; /* num of entries in words */ |
137 | u32 put; /* put for priv cmd queue */ | 137 | u32 put; /* put for priv cmd queue */ |
138 | u32 get; /* get for priv cmd queue */ | 138 | u32 get; /* get for priv cmd queue */ |
@@ -140,7 +140,7 @@ struct priv_cmd_queue { | |||
140 | 140 | ||
141 | struct priv_cmd_entry { | 141 | struct priv_cmd_entry { |
142 | bool valid; | 142 | bool valid; |
143 | struct mem_desc *mem; | 143 | struct nvgpu_mem *mem; |
144 | u32 off; /* offset in mem, in u32 entries */ | 144 | u32 off; /* offset in mem, in u32 entries */ |
145 | u64 gva; | 145 | u64 gva; |
146 | u32 get; /* start of entry in queue */ | 146 | u32 get; /* start of entry in queue */ |
@@ -335,24 +335,24 @@ struct mm_gk20a { | |||
335 | struct { | 335 | struct { |
336 | u32 aperture_size; | 336 | u32 aperture_size; |
337 | struct vm_gk20a vm; | 337 | struct vm_gk20a vm; |
338 | struct mem_desc inst_block; | 338 | struct nvgpu_mem inst_block; |
339 | } bar1; | 339 | } bar1; |
340 | 340 | ||
341 | struct { | 341 | struct { |
342 | u32 aperture_size; | 342 | u32 aperture_size; |
343 | struct vm_gk20a vm; | 343 | struct vm_gk20a vm; |
344 | struct mem_desc inst_block; | 344 | struct nvgpu_mem inst_block; |
345 | } bar2; | 345 | } bar2; |
346 | 346 | ||
347 | struct { | 347 | struct { |
348 | u32 aperture_size; | 348 | u32 aperture_size; |
349 | struct vm_gk20a vm; | 349 | struct vm_gk20a vm; |
350 | struct mem_desc inst_block; | 350 | struct nvgpu_mem inst_block; |
351 | } pmu; | 351 | } pmu; |
352 | 352 | ||
353 | struct { | 353 | struct { |
354 | /* using pmu vm currently */ | 354 | /* using pmu vm currently */ |
355 | struct mem_desc inst_block; | 355 | struct nvgpu_mem inst_block; |
356 | } hwpm; | 356 | } hwpm; |
357 | 357 | ||
358 | struct { | 358 | struct { |
@@ -367,7 +367,7 @@ struct mm_gk20a { | |||
367 | struct nvgpu_mutex tlb_lock; | 367 | struct nvgpu_mutex tlb_lock; |
368 | struct nvgpu_mutex priv_lock; | 368 | struct nvgpu_mutex priv_lock; |
369 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 369 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
370 | struct mem_desc bar2_desc; | 370 | struct nvgpu_mem bar2_desc; |
371 | #endif | 371 | #endif |
372 | /* | 372 | /* |
373 | * Separate function to cleanup the CE since it requires a channel to | 373 | * Separate function to cleanup the CE since it requires a channel to |
@@ -397,7 +397,7 @@ struct mm_gk20a { | |||
397 | /* false if vidmem aperture actually points to sysmem */ | 397 | /* false if vidmem aperture actually points to sysmem */ |
398 | bool vidmem_is_vidmem; | 398 | bool vidmem_is_vidmem; |
399 | 399 | ||
400 | struct mem_desc sysmem_flush; | 400 | struct nvgpu_mem sysmem_flush; |
401 | 401 | ||
402 | u32 pramin_window; | 402 | u32 pramin_window; |
403 | struct nvgpu_spinlock pramin_window_lock; | 403 | struct nvgpu_spinlock pramin_window_lock; |
@@ -475,11 +475,11 @@ struct nvgpu_page_alloc *get_vidmem_page_alloc(struct scatterlist *sgl); | |||
475 | #define bar1_instance_block_shift_gk20a() bus_bar1_block_ptr_shift_v() | 475 | #define bar1_instance_block_shift_gk20a() bus_bar1_block_ptr_shift_v() |
476 | #endif | 476 | #endif |
477 | 477 | ||
478 | int gk20a_alloc_inst_block(struct gk20a *g, struct mem_desc *inst_block); | 478 | int gk20a_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block); |
479 | void gk20a_free_inst_block(struct gk20a *g, struct mem_desc *inst_block); | 479 | void gk20a_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block); |
480 | void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, | 480 | void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, |
481 | u32 big_page_size); | 481 | u32 big_page_size); |
482 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct mem_desc *mem); | 482 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct nvgpu_mem *mem); |
483 | 483 | ||
484 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, | 484 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, |
485 | u64 va_begin, u64 va_end, char *label); | 485 | u64 va_begin, u64 va_end, char *label); |
@@ -499,7 +499,7 @@ void gk20a_free_sgtable(struct gk20a *g, struct sg_table **sgt); | |||
499 | u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, | 499 | u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, |
500 | u32 flags); | 500 | u32 flags); |
501 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); | 501 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); |
502 | u64 gk20a_mem_get_base_addr(struct gk20a *g, struct mem_desc *mem, | 502 | u64 gk20a_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem, |
503 | u32 flags); | 503 | u32 flags); |
504 | 504 | ||
505 | void gk20a_mm_ltc_isr(struct gk20a *g); | 505 | void gk20a_mm_ltc_isr(struct gk20a *g); |
@@ -542,39 +542,39 @@ u64 gk20a_gmmu_fixed_map(struct vm_gk20a *vm, | |||
542 | #define NVGPU_DMA_READ_ONLY (1 << 2) | 542 | #define NVGPU_DMA_READ_ONLY (1 << 2) |
543 | 543 | ||
544 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, size_t size, | 544 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, size_t size, |
545 | struct mem_desc *mem); | 545 | struct nvgpu_mem *mem); |
546 | int gk20a_gmmu_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, | 546 | int gk20a_gmmu_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, |
547 | size_t size, struct mem_desc *mem); | 547 | size_t size, struct nvgpu_mem *mem); |
548 | 548 | ||
549 | int gk20a_gmmu_alloc_map_sys(struct vm_gk20a *vm, size_t size, | 549 | int gk20a_gmmu_alloc_map_sys(struct vm_gk20a *vm, size_t size, |
550 | struct mem_desc *mem); | 550 | struct nvgpu_mem *mem); |
551 | int gk20a_gmmu_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags, | 551 | int gk20a_gmmu_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags, |
552 | size_t size, struct mem_desc *mem); | 552 | size_t size, struct nvgpu_mem *mem); |
553 | 553 | ||
554 | int gk20a_gmmu_alloc_map_vid(struct vm_gk20a *vm, size_t size, | 554 | int gk20a_gmmu_alloc_map_vid(struct vm_gk20a *vm, size_t size, |
555 | struct mem_desc *mem); | 555 | struct nvgpu_mem *mem); |
556 | int gk20a_gmmu_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags, | 556 | int gk20a_gmmu_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags, |
557 | size_t size, struct mem_desc *mem); | 557 | size_t size, struct nvgpu_mem *mem); |
558 | 558 | ||
559 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct mem_desc *mem); | 559 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem); |
560 | 560 | ||
561 | int gk20a_gmmu_alloc(struct gk20a *g, size_t size, struct mem_desc *mem); | 561 | int gk20a_gmmu_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem); |
562 | int gk20a_gmmu_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, | 562 | int gk20a_gmmu_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, |
563 | struct mem_desc *mem); | 563 | struct nvgpu_mem *mem); |
564 | 564 | ||
565 | int gk20a_gmmu_alloc_sys(struct gk20a *g, size_t size, struct mem_desc *mem); | 565 | int gk20a_gmmu_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem); |
566 | int gk20a_gmmu_alloc_flags_sys(struct gk20a *g, unsigned long flags, | 566 | int gk20a_gmmu_alloc_flags_sys(struct gk20a *g, unsigned long flags, |
567 | size_t size, struct mem_desc *mem); | 567 | size_t size, struct nvgpu_mem *mem); |
568 | 568 | ||
569 | int gk20a_gmmu_alloc_vid(struct gk20a *g, size_t size, struct mem_desc *mem); | 569 | int gk20a_gmmu_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem); |
570 | int gk20a_gmmu_alloc_flags_vid(struct gk20a *g, unsigned long flags, | 570 | int gk20a_gmmu_alloc_flags_vid(struct gk20a *g, unsigned long flags, |
571 | size_t size, struct mem_desc *mem); | 571 | size_t size, struct nvgpu_mem *mem); |
572 | int gk20a_gmmu_alloc_flags_vid_at(struct gk20a *g, unsigned long flags, | 572 | int gk20a_gmmu_alloc_flags_vid_at(struct gk20a *g, unsigned long flags, |
573 | size_t size, struct mem_desc *mem, dma_addr_t at); | 573 | size_t size, struct nvgpu_mem *mem, dma_addr_t at); |
574 | 574 | ||
575 | void gk20a_gmmu_free(struct gk20a *g, struct mem_desc *mem); | 575 | void gk20a_gmmu_free(struct gk20a *g, struct nvgpu_mem *mem); |
576 | 576 | ||
577 | static inline phys_addr_t gk20a_mem_phys(struct mem_desc *mem) | 577 | static inline phys_addr_t gk20a_mem_phys(struct nvgpu_mem *mem) |
578 | { | 578 | { |
579 | /* FIXME: the sgt/sgl may get null if this is accessed e.g. in an isr | 579 | /* FIXME: the sgt/sgl may get null if this is accessed e.g. in an isr |
580 | * during channel deletion - attempt to fix at least null derefs */ | 580 | * during channel deletion - attempt to fix at least null derefs */ |
@@ -591,7 +591,7 @@ static inline phys_addr_t gk20a_mem_phys(struct mem_desc *mem) | |||
591 | 591 | ||
592 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | 592 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, |
593 | u32 sysmem_mask, u32 vidmem_mask); | 593 | u32 sysmem_mask, u32 vidmem_mask); |
594 | u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem, | 594 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, |
595 | u32 sysmem_mask, u32 vidmem_mask); | 595 | u32 sysmem_mask, u32 vidmem_mask); |
596 | 596 | ||
597 | void gk20a_pde_wr32(struct gk20a *g, struct gk20a_mm_entry *entry, | 597 | void gk20a_pde_wr32(struct gk20a *g, struct gk20a_mm_entry *entry, |
@@ -769,10 +769,10 @@ struct gpu_ops; | |||
769 | void gk20a_init_mm(struct gpu_ops *gops); | 769 | void gk20a_init_mm(struct gpu_ops *gops); |
770 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, | 770 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, |
771 | u32 big_page_size); | 771 | u32 big_page_size); |
772 | void gk20a_mm_init_pdb(struct gk20a *g, struct mem_desc *mem, | 772 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem, |
773 | struct vm_gk20a *vm); | 773 | struct vm_gk20a *vm); |
774 | 774 | ||
775 | void gk20a_remove_vm(struct vm_gk20a *vm, struct mem_desc *inst_block); | 775 | void gk20a_remove_vm(struct vm_gk20a *vm, struct nvgpu_mem *inst_block); |
776 | 776 | ||
777 | int gk20a_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size); | 777 | int gk20a_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size); |
778 | 778 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index e70e50c2..591b7163 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -4743,7 +4743,7 @@ clean_up: | |||
4743 | return err; | 4743 | return err; |
4744 | } | 4744 | } |
4745 | 4745 | ||
4746 | void gk20a_pmu_surface_describe(struct gk20a *g, struct mem_desc *mem, | 4746 | void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem, |
4747 | struct flcn_mem_desc_v0 *fb) | 4747 | struct flcn_mem_desc_v0 *fb) |
4748 | { | 4748 | { |
4749 | fb->address.lo = u64_lo32(mem->gpu_va); | 4749 | fb->address.lo = u64_lo32(mem->gpu_va); |
@@ -4752,7 +4752,7 @@ void gk20a_pmu_surface_describe(struct gk20a *g, struct mem_desc *mem, | |||
4752 | fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24); | 4752 | fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24); |
4753 | } | 4753 | } |
4754 | 4754 | ||
4755 | int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 4755 | int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, |
4756 | u32 size) | 4756 | u32 size) |
4757 | { | 4757 | { |
4758 | struct mm_gk20a *mm = &g->mm; | 4758 | struct mm_gk20a *mm = &g->mm; |
@@ -4768,7 +4768,7 @@ int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | |||
4768 | return 0; | 4768 | return 0; |
4769 | } | 4769 | } |
4770 | 4770 | ||
4771 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 4771 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, |
4772 | u32 size) | 4772 | u32 size) |
4773 | { | 4773 | { |
4774 | struct mm_gk20a *mm = &g->mm; | 4774 | struct mm_gk20a *mm = &g->mm; |
@@ -4784,10 +4784,10 @@ int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | |||
4784 | return 0; | 4784 | return 0; |
4785 | } | 4785 | } |
4786 | 4786 | ||
4787 | void gk20a_pmu_surface_free(struct gk20a *g, struct mem_desc *mem) | 4787 | void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem) |
4788 | { | 4788 | { |
4789 | gk20a_gmmu_free(g, mem); | 4789 | gk20a_gmmu_free(g, mem); |
4790 | memset(mem, 0, sizeof(struct mem_desc)); | 4790 | memset(mem, 0, sizeof(struct nvgpu_mem)); |
4791 | } | 4791 | } |
4792 | 4792 | ||
4793 | int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | 4793 | int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, |
@@ -4860,7 +4860,8 @@ int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
4860 | goto clean_up; | 4860 | goto clean_up; |
4861 | 4861 | ||
4862 | if (payload->in.fb_size != 0x0) { | 4862 | if (payload->in.fb_size != 0x0) { |
4863 | seq->in_mem = nvgpu_kzalloc(g, sizeof(struct mem_desc)); | 4863 | seq->in_mem = nvgpu_kzalloc(g, |
4864 | sizeof(struct nvgpu_mem)); | ||
4864 | if (!seq->in_mem) { | 4865 | if (!seq->in_mem) { |
4865 | err = -ENOMEM; | 4866 | err = -ENOMEM; |
4866 | goto clean_up; | 4867 | goto clean_up; |
@@ -4904,7 +4905,7 @@ int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
4904 | 4905 | ||
4905 | if (payload->out.fb_size != 0x0) { | 4906 | if (payload->out.fb_size != 0x0) { |
4906 | seq->out_mem = nvgpu_kzalloc(g, | 4907 | seq->out_mem = nvgpu_kzalloc(g, |
4907 | sizeof(struct mem_desc)); | 4908 | sizeof(struct nvgpu_mem)); |
4908 | if (!seq->out_mem) { | 4909 | if (!seq->out_mem) { |
4909 | err = -ENOMEM; | 4910 | err = -ENOMEM; |
4910 | goto clean_up; | 4911 | goto clean_up; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 88649d8e..84161304 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -185,8 +185,8 @@ struct pmu_payload { | |||
185 | }; | 185 | }; |
186 | 186 | ||
187 | struct pmu_surface { | 187 | struct pmu_surface { |
188 | struct mem_desc vidmem_desc; | 188 | struct nvgpu_mem vidmem_desc; |
189 | struct mem_desc sysmem_desc; | 189 | struct nvgpu_mem sysmem_desc; |
190 | struct flcn_mem_desc_v0 params; | 190 | struct flcn_mem_desc_v0 params; |
191 | }; | 191 | }; |
192 | 192 | ||
@@ -204,14 +204,14 @@ struct pmu_sequence { | |||
204 | struct pmu_allocation_v2 in_v2; | 204 | struct pmu_allocation_v2 in_v2; |
205 | struct pmu_allocation_v3 in_v3; | 205 | struct pmu_allocation_v3 in_v3; |
206 | }; | 206 | }; |
207 | struct mem_desc *in_mem; | 207 | struct nvgpu_mem *in_mem; |
208 | union { | 208 | union { |
209 | struct pmu_allocation_v0 out_v0; | 209 | struct pmu_allocation_v0 out_v0; |
210 | struct pmu_allocation_v1 out_v1; | 210 | struct pmu_allocation_v1 out_v1; |
211 | struct pmu_allocation_v2 out_v2; | 211 | struct pmu_allocation_v2 out_v2; |
212 | struct pmu_allocation_v3 out_v3; | 212 | struct pmu_allocation_v3 out_v3; |
213 | }; | 213 | }; |
214 | struct mem_desc *out_mem; | 214 | struct nvgpu_mem *out_mem; |
215 | u8 *out_payload; | 215 | u8 *out_payload; |
216 | pmu_callback callback; | 216 | pmu_callback callback; |
217 | void* cb_params; | 217 | void* cb_params; |
@@ -314,13 +314,13 @@ struct pmu_gk20a { | |||
314 | struct pmu_ucode_desc *desc; | 314 | struct pmu_ucode_desc *desc; |
315 | struct pmu_ucode_desc_v1 *desc_v1; | 315 | struct pmu_ucode_desc_v1 *desc_v1; |
316 | }; | 316 | }; |
317 | struct mem_desc ucode; | 317 | struct nvgpu_mem ucode; |
318 | 318 | ||
319 | struct mem_desc pg_buf; | 319 | struct nvgpu_mem pg_buf; |
320 | /* TBD: remove this if ZBC seq is fixed */ | 320 | /* TBD: remove this if ZBC seq is fixed */ |
321 | struct mem_desc seq_buf; | 321 | struct nvgpu_mem seq_buf; |
322 | struct mem_desc trace_buf; | 322 | struct nvgpu_mem trace_buf; |
323 | struct mem_desc wpr_buf; | 323 | struct nvgpu_mem wpr_buf; |
324 | bool buf_loaded; | 324 | bool buf_loaded; |
325 | 325 | ||
326 | struct pmu_sha1_gid gid_info; | 326 | struct pmu_sha1_gid gid_info; |
@@ -459,12 +459,12 @@ int gk20a_pmu_reset(struct gk20a *g); | |||
459 | int pmu_idle(struct pmu_gk20a *pmu); | 459 | int pmu_idle(struct pmu_gk20a *pmu); |
460 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable); | 460 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable); |
461 | 461 | ||
462 | void gk20a_pmu_surface_free(struct gk20a *g, struct mem_desc *mem); | 462 | void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem); |
463 | void gk20a_pmu_surface_describe(struct gk20a *g, struct mem_desc *mem, | 463 | void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem, |
464 | struct flcn_mem_desc_v0 *fb); | 464 | struct flcn_mem_desc_v0 *fb); |
465 | int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 465 | int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, |
466 | u32 size); | 466 | u32 size); |
467 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 467 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, |
468 | u32 size); | 468 | u32 size); |
469 | 469 | ||
470 | #endif /*__PMU_GK20A_H__*/ | 470 | #endif /*__PMU_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c index 7e6005a2..9106bbe0 100644 --- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | 24 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> |
25 | 25 | ||
26 | /* WARNING: returns pramin_window_lock taken, complement with pramin_exit() */ | 26 | /* WARNING: returns pramin_window_lock taken, complement with pramin_exit() */ |
27 | static u32 gk20a_pramin_enter(struct gk20a *g, struct mem_desc *mem, | 27 | static u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem, |
28 | struct page_alloc_chunk *chunk, u32 w) | 28 | struct page_alloc_chunk *chunk, u32 w) |
29 | { | 29 | { |
30 | u64 bufbase = chunk->base; | 30 | u64 bufbase = chunk->base; |
@@ -55,7 +55,7 @@ static u32 gk20a_pramin_enter(struct gk20a *g, struct mem_desc *mem, | |||
55 | return lo; | 55 | return lo; |
56 | } | 56 | } |
57 | 57 | ||
58 | static void gk20a_pramin_exit(struct gk20a *g, struct mem_desc *mem, | 58 | static void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem, |
59 | struct page_alloc_chunk *chunk) | 59 | struct page_alloc_chunk *chunk) |
60 | { | 60 | { |
61 | gk20a_dbg(gpu_dbg_mem, "end for %p,%p", mem, chunk); | 61 | gk20a_dbg(gpu_dbg_mem, "end for %p,%p", mem, chunk); |