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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h6
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 7106ea03..65197aca 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -137,8 +137,8 @@ int gk20a_prepare_poweroff(struct gk20a *g)
137 ret |= gk20a_mm_suspend(g); 137 ret |= gk20a_mm_suspend(g);
138 ret |= gk20a_fifo_suspend(g); 138 ret |= gk20a_fifo_suspend(g);
139 139
140 if (g->ops.pmu.mclk_deinit) 140 if (g->ops.clk.mclk_deinit)
141 g->ops.pmu.mclk_deinit(g); 141 g->ops.clk.mclk_deinit(g);
142 142
143 /* Disable GPCPLL */ 143 /* Disable GPCPLL */
144 if (g->ops.clk.suspend_clk_support) 144 if (g->ops.clk.suspend_clk_support)
@@ -273,8 +273,8 @@ int gk20a_finalize_poweron(struct gk20a *g)
273 goto done; 273 goto done;
274 } 274 }
275 275
276 if (g->ops.pmu.mclk_init) { 276 if (g->ops.clk.mclk_init) {
277 err = g->ops.pmu.mclk_init(g); 277 err = g->ops.clk.mclk_init(g);
278 if (err) { 278 if (err) {
279 nvgpu_err(g, "failed to set mclk"); 279 nvgpu_err(g, "failed to set mclk");
280 /* Indicate error dont goto done */ 280 /* Indicate error dont goto done */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 06db2b7f..9b28e0c6 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -772,9 +772,6 @@ struct gpu_ops {
772 void *lsfm, u32 *p_bl_gen_desc_size); 772 void *lsfm, u32 *p_bl_gen_desc_size);
773 int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, 773 int (*flcn_populate_bl_dmem_desc)(struct gk20a *g,
774 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); 774 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
775 int (*mclk_init)(struct gk20a *g);
776 void (*mclk_deinit)(struct gk20a *g);
777 int (*mclk_change)(struct gk20a *g, u16 val);
778 void (*handle_ext_irq)(struct gk20a *g, u32 intr); 775 void (*handle_ext_irq)(struct gk20a *g, u32 intr);
779 void (*set_irqmask)(struct gk20a *g); 776 void (*set_irqmask)(struct gk20a *g);
780 u32 lspmuwprinitdone; 777 u32 lspmuwprinitdone;
@@ -802,6 +799,9 @@ struct gpu_ops {
802 int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val); 799 int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val);
803 int (*get_pll_debug_data)(struct gk20a *g, 800 int (*get_pll_debug_data)(struct gk20a *g,
804 struct nvgpu_clk_pll_debug_data *d); 801 struct nvgpu_clk_pll_debug_data *d);
802 int (*mclk_init)(struct gk20a *g);
803 void (*mclk_deinit)(struct gk20a *g);
804 int (*mclk_change)(struct gk20a *g, u16 val);
805 } clk; 805 } clk;
806 struct { 806 struct {
807 u32 (*get_arbiter_clk_domains)(struct gk20a *g); 807 u32 (*get_arbiter_clk_domains)(struct gk20a *g);