diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 |
3 files changed, 2 insertions, 108 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index cac62db7..a4becda0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -65,32 +65,6 @@ void __nvgpu_check_gpu_state(struct gk20a *g) | |||
65 | } | 65 | } |
66 | } | 66 | } |
67 | 67 | ||
68 | /* | ||
69 | * Locks out the driver from accessing GPU registers. This prevents access to | ||
70 | * thse registers after the GPU has been clock or power gated. This should help | ||
71 | * find annoying bugs where register reads and writes are silently dropped | ||
72 | * after the GPU has been turned off. On older chips these reads and writes can | ||
73 | * also lock the entire CPU up. | ||
74 | */ | ||
75 | int gk20a_lockout_registers(struct gk20a *g) | ||
76 | { | ||
77 | g->regs = NULL; | ||
78 | g->bar1 = NULL; | ||
79 | |||
80 | return 0; | ||
81 | } | ||
82 | |||
83 | /* | ||
84 | * Undoes gk20a_lockout_registers(). | ||
85 | */ | ||
86 | int gk20a_restore_registers(struct gk20a *g) | ||
87 | { | ||
88 | g->regs = g->regs_saved; | ||
89 | g->bar1 = g->bar1_saved; | ||
90 | |||
91 | return 0; | ||
92 | } | ||
93 | |||
94 | void __gk20a_warn_on_no_regs(void) | 68 | void __gk20a_warn_on_no_regs(void) |
95 | { | 69 | { |
96 | WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); | 70 | WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a45a7b4e..bf10055a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -44,6 +44,7 @@ struct nvgpu_mem_sgt; | |||
44 | 44 | ||
45 | #include <nvgpu/lock.h> | 45 | #include <nvgpu/lock.h> |
46 | #include <nvgpu/thread.h> | 46 | #include <nvgpu/thread.h> |
47 | #include <nvgpu/io.h> | ||
47 | #ifdef CONFIG_DEBUG_FS | 48 | #ifdef CONFIG_DEBUG_FS |
48 | #include <linux/debugfs.h> | 49 | #include <linux/debugfs.h> |
49 | #endif | 50 | #endif |
@@ -1067,14 +1068,6 @@ struct gk20a { | |||
1067 | 1068 | ||
1068 | struct nvgpu_ref refcount; | 1069 | struct nvgpu_ref refcount; |
1069 | 1070 | ||
1070 | struct resource *reg_mem; | ||
1071 | void __iomem *regs; | ||
1072 | void __iomem *regs_saved; | ||
1073 | |||
1074 | struct resource *bar1_mem; | ||
1075 | void __iomem *bar1; | ||
1076 | void __iomem *bar1_saved; | ||
1077 | |||
1078 | const char *name; | 1071 | const char *name; |
1079 | 1072 | ||
1080 | bool gpu_reset_done; | 1073 | bool gpu_reset_done; |
@@ -1339,81 +1332,9 @@ enum gk20a_nonstall_ops { | |||
1339 | }; | 1332 | }; |
1340 | 1333 | ||
1341 | /* register accessors */ | 1334 | /* register accessors */ |
1342 | int gk20a_lockout_registers(struct gk20a *g); | ||
1343 | int gk20a_restore_registers(struct gk20a *g); | ||
1344 | |||
1345 | void __nvgpu_check_gpu_state(struct gk20a *g); | 1335 | void __nvgpu_check_gpu_state(struct gk20a *g); |
1346 | void __gk20a_warn_on_no_regs(void); | 1336 | void __gk20a_warn_on_no_regs(void); |
1347 | 1337 | ||
1348 | static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v) | ||
1349 | { | ||
1350 | if (unlikely(!g->regs)) { | ||
1351 | __gk20a_warn_on_no_regs(); | ||
1352 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); | ||
1353 | } else { | ||
1354 | writel_relaxed(v, g->regs + r); | ||
1355 | nvgpu_smp_wmb(); | ||
1356 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); | ||
1357 | } | ||
1358 | } | ||
1359 | static inline u32 gk20a_readl(struct gk20a *g, u32 r) | ||
1360 | { | ||
1361 | |||
1362 | u32 v = 0xffffffff; | ||
1363 | |||
1364 | if (unlikely(!g->regs)) { | ||
1365 | __gk20a_warn_on_no_regs(); | ||
1366 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); | ||
1367 | } else { | ||
1368 | v = readl(g->regs + r); | ||
1369 | if (v == 0xffffffff) | ||
1370 | __nvgpu_check_gpu_state(g); | ||
1371 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); | ||
1372 | } | ||
1373 | |||
1374 | return v; | ||
1375 | } | ||
1376 | static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v) | ||
1377 | { | ||
1378 | if (unlikely(!g->regs)) { | ||
1379 | __gk20a_warn_on_no_regs(); | ||
1380 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); | ||
1381 | } else { | ||
1382 | nvgpu_smp_wmb(); | ||
1383 | do { | ||
1384 | writel_relaxed(v, g->regs + r); | ||
1385 | } while (readl(g->regs + r) != v); | ||
1386 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); | ||
1387 | } | ||
1388 | } | ||
1389 | |||
1390 | static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v) | ||
1391 | { | ||
1392 | if (unlikely(!g->bar1)) { | ||
1393 | __gk20a_warn_on_no_regs(); | ||
1394 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); | ||
1395 | } else { | ||
1396 | nvgpu_smp_wmb(); | ||
1397 | writel_relaxed(v, g->bar1 + b); | ||
1398 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); | ||
1399 | } | ||
1400 | } | ||
1401 | |||
1402 | static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b) | ||
1403 | { | ||
1404 | u32 v = 0xffffffff; | ||
1405 | |||
1406 | if (unlikely(!g->bar1)) { | ||
1407 | __gk20a_warn_on_no_regs(); | ||
1408 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); | ||
1409 | } else { | ||
1410 | v = readl(g->bar1 + b); | ||
1411 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); | ||
1412 | } | ||
1413 | |||
1414 | return v; | ||
1415 | } | ||
1416 | |||
1417 | /* convenience */ | 1338 | /* convenience */ |
1418 | static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) | 1339 | static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) |
1419 | { | 1340 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 707bfb87..6f829282 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5256,8 +5256,7 @@ static inline bool is_valid_cyclestats_bar0_offset_gk20a(struct gk20a *g, | |||
5256 | is_bar0_global_offset_whitelisted_gk20a(g, offset); | 5256 | is_bar0_global_offset_whitelisted_gk20a(g, offset); |
5257 | /* resource size check in case there was a problem | 5257 | /* resource size check in case there was a problem |
5258 | * with allocating the assumed size of bar0 */ | 5258 | * with allocating the assumed size of bar0 */ |
5259 | valid = valid && | 5259 | valid = valid && gk20a_io_valid_reg(g, offset); |
5260 | offset < resource_size(g->regs); | ||
5261 | return valid; | 5260 | return valid; |
5262 | } | 5261 | } |
5263 | #endif | 5262 | #endif |