diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 65 |
1 files changed, 42 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index bdcf750e..8ef7d04d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5858,7 +5858,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5858 | struct gr_gk20a_isr_data isr_data; | 5858 | struct gr_gk20a_isr_data isr_data; |
5859 | u32 grfifo_ctl; | 5859 | u32 grfifo_ctl; |
5860 | u32 obj_table; | 5860 | u32 obj_table; |
5861 | int need_reset = 0; | 5861 | bool need_reset = false; |
5862 | u32 gr_intr = gk20a_readl(g, gr_intr_r()); | 5862 | u32 gr_intr = gk20a_readl(g, gr_intr_r()); |
5863 | struct channel_gk20a *ch = NULL; | 5863 | struct channel_gk20a *ch = NULL; |
5864 | struct channel_gk20a *fault_ch = NULL; | 5864 | struct channel_gk20a *fault_ch = NULL; |
@@ -5931,44 +5931,56 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5931 | } | 5931 | } |
5932 | 5932 | ||
5933 | if (gr_intr & gr_intr_semaphore_timeout_pending_f()) { | 5933 | if (gr_intr & gr_intr_semaphore_timeout_pending_f()) { |
5934 | need_reset |= gk20a_gr_handle_semaphore_timeout_pending(g, | 5934 | if (gk20a_gr_handle_semaphore_timeout_pending(g, |
5935 | &isr_data); | 5935 | &isr_data) != 0) { |
5936 | need_reset = true; | ||
5937 | } | ||
5936 | gk20a_writel(g, gr_intr_r(), | 5938 | gk20a_writel(g, gr_intr_r(), |
5937 | gr_intr_semaphore_reset_f()); | 5939 | gr_intr_semaphore_reset_f()); |
5938 | gr_intr &= ~gr_intr_semaphore_pending_f(); | 5940 | gr_intr &= ~gr_intr_semaphore_pending_f(); |
5939 | } | 5941 | } |
5940 | 5942 | ||
5941 | if (gr_intr & gr_intr_illegal_notify_pending_f()) { | 5943 | if (gr_intr & gr_intr_illegal_notify_pending_f()) { |
5942 | need_reset |= gk20a_gr_intr_illegal_notify_pending(g, | 5944 | if (gk20a_gr_intr_illegal_notify_pending(g, |
5943 | &isr_data); | 5945 | &isr_data) != 0) { |
5946 | need_reset = true; | ||
5947 | } | ||
5944 | gk20a_writel(g, gr_intr_r(), | 5948 | gk20a_writel(g, gr_intr_r(), |
5945 | gr_intr_illegal_notify_reset_f()); | 5949 | gr_intr_illegal_notify_reset_f()); |
5946 | gr_intr &= ~gr_intr_illegal_notify_pending_f(); | 5950 | gr_intr &= ~gr_intr_illegal_notify_pending_f(); |
5947 | } | 5951 | } |
5948 | 5952 | ||
5949 | if (gr_intr & gr_intr_illegal_method_pending_f()) { | 5953 | if (gr_intr & gr_intr_illegal_method_pending_f()) { |
5950 | need_reset |= gk20a_gr_handle_illegal_method(g, &isr_data); | 5954 | if (gk20a_gr_handle_illegal_method(g, &isr_data) != 0) { |
5955 | need_reset = true; | ||
5956 | } | ||
5951 | gk20a_writel(g, gr_intr_r(), | 5957 | gk20a_writel(g, gr_intr_r(), |
5952 | gr_intr_illegal_method_reset_f()); | 5958 | gr_intr_illegal_method_reset_f()); |
5953 | gr_intr &= ~gr_intr_illegal_method_pending_f(); | 5959 | gr_intr &= ~gr_intr_illegal_method_pending_f(); |
5954 | } | 5960 | } |
5955 | 5961 | ||
5956 | if (gr_intr & gr_intr_illegal_class_pending_f()) { | 5962 | if (gr_intr & gr_intr_illegal_class_pending_f()) { |
5957 | need_reset |= gk20a_gr_handle_illegal_class(g, &isr_data); | 5963 | if (gk20a_gr_handle_illegal_class(g, &isr_data) != 0) { |
5964 | need_reset = true; | ||
5965 | } | ||
5958 | gk20a_writel(g, gr_intr_r(), | 5966 | gk20a_writel(g, gr_intr_r(), |
5959 | gr_intr_illegal_class_reset_f()); | 5967 | gr_intr_illegal_class_reset_f()); |
5960 | gr_intr &= ~gr_intr_illegal_class_pending_f(); | 5968 | gr_intr &= ~gr_intr_illegal_class_pending_f(); |
5961 | } | 5969 | } |
5962 | 5970 | ||
5963 | if (gr_intr & gr_intr_fecs_error_pending_f()) { | 5971 | if (gr_intr & gr_intr_fecs_error_pending_f()) { |
5964 | need_reset |= g->ops.gr.handle_fecs_error(g, ch, &isr_data); | 5972 | if (g->ops.gr.handle_fecs_error(g, ch, &isr_data) != 0) { |
5973 | need_reset = true; | ||
5974 | } | ||
5965 | gk20a_writel(g, gr_intr_r(), | 5975 | gk20a_writel(g, gr_intr_r(), |
5966 | gr_intr_fecs_error_reset_f()); | 5976 | gr_intr_fecs_error_reset_f()); |
5967 | gr_intr &= ~gr_intr_fecs_error_pending_f(); | 5977 | gr_intr &= ~gr_intr_fecs_error_pending_f(); |
5968 | } | 5978 | } |
5969 | 5979 | ||
5970 | if (gr_intr & gr_intr_class_error_pending_f()) { | 5980 | if (gr_intr & gr_intr_class_error_pending_f()) { |
5971 | need_reset |= gk20a_gr_handle_class_error(g, &isr_data); | 5981 | if (gk20a_gr_handle_class_error(g, &isr_data) != 0) { |
5982 | need_reset = true; | ||
5983 | } | ||
5972 | gk20a_writel(g, gr_intr_r(), | 5984 | gk20a_writel(g, gr_intr_r(), |
5973 | gr_intr_class_error_reset_f()); | 5985 | gr_intr_class_error_reset_f()); |
5974 | gr_intr &= ~gr_intr_class_error_pending_f(); | 5986 | gr_intr &= ~gr_intr_class_error_pending_f(); |
@@ -5977,7 +5989,9 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5977 | /* this one happens if someone tries to hit a non-whitelisted | 5989 | /* this one happens if someone tries to hit a non-whitelisted |
5978 | * register using set_falcon[4] */ | 5990 | * register using set_falcon[4] */ |
5979 | if (gr_intr & gr_intr_firmware_method_pending_f()) { | 5991 | if (gr_intr & gr_intr_firmware_method_pending_f()) { |
5980 | need_reset |= gk20a_gr_handle_firmware_method(g, &isr_data); | 5992 | if (gk20a_gr_handle_firmware_method(g, &isr_data) != 0) { |
5993 | need_reset = true; | ||
5994 | } | ||
5981 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "firmware method intr pending\n"); | 5995 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "firmware method intr pending\n"); |
5982 | gk20a_writel(g, gr_intr_r(), | 5996 | gk20a_writel(g, gr_intr_r(), |
5983 | gr_intr_firmware_method_reset_f()); | 5997 | gr_intr_firmware_method_reset_f()); |
@@ -5997,7 +6011,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5997 | fe, info); | 6011 | fe, info); |
5998 | gk20a_writel(g, gr_fe_hww_esr_r(), | 6012 | gk20a_writel(g, gr_fe_hww_esr_r(), |
5999 | gr_fe_hww_esr_reset_active_f()); | 6013 | gr_fe_hww_esr_reset_active_f()); |
6000 | need_reset |= -EFAULT; | 6014 | need_reset = true; |
6001 | } | 6015 | } |
6002 | 6016 | ||
6003 | if (exception & gr_exception_memfmt_m()) { | 6017 | if (exception & gr_exception_memfmt_m()) { |
@@ -6006,7 +6020,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6006 | nvgpu_err(g, "memfmt exception: esr %08x", memfmt); | 6020 | nvgpu_err(g, "memfmt exception: esr %08x", memfmt); |
6007 | gk20a_writel(g, gr_memfmt_hww_esr_r(), | 6021 | gk20a_writel(g, gr_memfmt_hww_esr_r(), |
6008 | gr_memfmt_hww_esr_reset_active_f()); | 6022 | gr_memfmt_hww_esr_reset_active_f()); |
6009 | need_reset |= -EFAULT; | 6023 | need_reset = true; |
6010 | } | 6024 | } |
6011 | 6025 | ||
6012 | if (exception & gr_exception_pd_m()) { | 6026 | if (exception & gr_exception_pd_m()) { |
@@ -6015,7 +6029,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6015 | nvgpu_err(g, "pd exception: esr 0x%08x", pd); | 6029 | nvgpu_err(g, "pd exception: esr 0x%08x", pd); |
6016 | gk20a_writel(g, gr_pd_hww_esr_r(), | 6030 | gk20a_writel(g, gr_pd_hww_esr_r(), |
6017 | gr_pd_hww_esr_reset_active_f()); | 6031 | gr_pd_hww_esr_reset_active_f()); |
6018 | need_reset |= -EFAULT; | 6032 | need_reset = true; |
6019 | } | 6033 | } |
6020 | 6034 | ||
6021 | if (exception & gr_exception_scc_m()) { | 6035 | if (exception & gr_exception_scc_m()) { |
@@ -6024,7 +6038,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6024 | nvgpu_err(g, "scc exception: esr 0x%08x", scc); | 6038 | nvgpu_err(g, "scc exception: esr 0x%08x", scc); |
6025 | gk20a_writel(g, gr_scc_hww_esr_r(), | 6039 | gk20a_writel(g, gr_scc_hww_esr_r(), |
6026 | gr_scc_hww_esr_reset_active_f()); | 6040 | gr_scc_hww_esr_reset_active_f()); |
6027 | need_reset |= -EFAULT; | 6041 | need_reset = true; |
6028 | } | 6042 | } |
6029 | 6043 | ||
6030 | if (exception & gr_exception_ds_m()) { | 6044 | if (exception & gr_exception_ds_m()) { |
@@ -6033,14 +6047,17 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6033 | nvgpu_err(g, "ds exception: esr: 0x%08x", ds); | 6047 | nvgpu_err(g, "ds exception: esr: 0x%08x", ds); |
6034 | gk20a_writel(g, gr_ds_hww_esr_r(), | 6048 | gk20a_writel(g, gr_ds_hww_esr_r(), |
6035 | gr_ds_hww_esr_reset_task_f()); | 6049 | gr_ds_hww_esr_reset_task_f()); |
6036 | need_reset |= -EFAULT; | 6050 | need_reset = true; |
6037 | } | 6051 | } |
6038 | 6052 | ||
6039 | if (exception & gr_exception_ssync_m()) { | 6053 | if (exception & gr_exception_ssync_m()) { |
6040 | if (g->ops.gr.handle_ssync_hww) | 6054 | if (g->ops.gr.handle_ssync_hww) { |
6041 | need_reset |= g->ops.gr.handle_ssync_hww(g); | 6055 | if (g->ops.gr.handle_ssync_hww(g) != 0) { |
6042 | else | 6056 | need_reset = true; |
6057 | } | ||
6058 | } else { | ||
6043 | nvgpu_err(g, "unhandled ssync exception"); | 6059 | nvgpu_err(g, "unhandled ssync exception"); |
6060 | } | ||
6044 | } | 6061 | } |
6045 | 6062 | ||
6046 | if (exception & gr_exception_mme_m()) { | 6063 | if (exception & gr_exception_mme_m()) { |
@@ -6051,7 +6068,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6051 | mme, info); | 6068 | mme, info); |
6052 | gk20a_writel(g, gr_mme_hww_esr_r(), | 6069 | gk20a_writel(g, gr_mme_hww_esr_r(), |
6053 | gr_mme_hww_esr_reset_active_f()); | 6070 | gr_mme_hww_esr_reset_active_f()); |
6054 | need_reset |= -EFAULT; | 6071 | need_reset = true; |
6055 | } | 6072 | } |
6056 | 6073 | ||
6057 | if (exception & gr_exception_sked_m()) { | 6074 | if (exception & gr_exception_sked_m()) { |
@@ -6060,11 +6077,11 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6060 | nvgpu_err(g, "sked exception: esr 0x%08x", sked); | 6077 | nvgpu_err(g, "sked exception: esr 0x%08x", sked); |
6061 | gk20a_writel(g, gr_sked_hww_esr_r(), | 6078 | gk20a_writel(g, gr_sked_hww_esr_r(), |
6062 | gr_sked_hww_esr_reset_active_f()); | 6079 | gr_sked_hww_esr_reset_active_f()); |
6063 | need_reset |= -EFAULT; | 6080 | need_reset = true; |
6064 | } | 6081 | } |
6065 | 6082 | ||
6066 | /* check if a gpc exception has occurred */ | 6083 | /* check if a gpc exception has occurred */ |
6067 | if (exception & gr_exception_gpc_m() && need_reset == 0) { | 6084 | if (exception & gr_exception_gpc_m() && !need_reset) { |
6068 | bool post_event = false; | 6085 | bool post_event = false; |
6069 | 6086 | ||
6070 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 6087 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
@@ -6075,8 +6092,10 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6075 | 6092 | ||
6076 | /*isr_data.chid can be ~0 and fault_ch can be NULL */ | 6093 | /*isr_data.chid can be ~0 and fault_ch can be NULL */ |
6077 | /* check if any gpc has an exception */ | 6094 | /* check if any gpc has an exception */ |
6078 | need_reset |= gk20a_gr_handle_gpc_exception(g, | 6095 | if (gk20a_gr_handle_gpc_exception(g, &post_event, |
6079 | &post_event, fault_ch, &global_esr); | 6096 | fault_ch, &global_esr) != 0) { |
6097 | need_reset = true; | ||
6098 | } | ||
6080 | 6099 | ||
6081 | /* signal clients waiting on an event */ | 6100 | /* signal clients waiting on an event */ |
6082 | if (g->ops.gr.sm_debugger_attached(g) && | 6101 | if (g->ops.gr.sm_debugger_attached(g) && |