7 files changed, 110 insertions, 28 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index ebe2dca4..c9f84041 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -63,6 +63,9 @@
 #include "hal.h"
 #include "vgpu/vgpu.h"
 #include "pci.h"
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+#include "pstate/pstate.h"
+#endif
 
 #define CREATE_TRACE_POINTS
 #include <trace/events/gk20a.h>
@@ -956,6 +959,16 @@ int gk20a_pm_finalize_poweron(struct device *dev)
                 goto done;
         }
 
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+        if (g->ops.pmupstate) {
+                err = gk20a_init_pstate_support(g);
+                if (err) {
+                        gk20a_err(dev, "failed to init pstates");
+                        goto done;
+                }
+        }
+#endif
+
         err = gk20a_init_pmu_support(g);
         if (err) {
                 gk20a_err(dev, "failed to init gk20a pmu");
@@ -968,6 +981,16 @@ int gk20a_pm_finalize_poweron(struct device *dev)
                 goto done;
         }
 
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+        if (g->ops.pmupstate) {
+                err = gk20a_init_pstate_pmu_support(g);
+                if (err) {
+                        gk20a_err(dev, "failed to init pstates");
+                        goto done;
+                }
+        }
+#endif
+
         if (g->ops.pmu.mclk_init) {
                 err = g->ops.pmu.mclk_init(g);
                 if (err) {
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c4744f3c..edc4a0e1 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -54,6 +54,11 @@ struct acr_desc;
 #include "debug_gk20a.h"
 #include "sched_gk20a.h"
 #include "gm206/bios_gm206.h"
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+#include "clk/clk.h"
+#include "perf/perf.h"
+#endif
+#include "gm206/bios_gm206.h"
 
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
     32 ns is the resolution of ptimer. */
@@ -607,6 +612,7 @@ struct gpu_ops {
         } clk;
         bool privsecurity;
         bool securegpccs;
+        bool pmupstate;
         struct {
                 const struct regop_offset_range* (
                                 *get_global_whitelist_ranges)(void);
@@ -717,6 +723,7 @@ struct nvgpu_bios {
 
         struct bit_token *perf_token;
         struct bit_token *clock_token;
+        struct bit_token *virt_token;
         u32 expansion_rom_offset;
 };
 
@@ -746,6 +753,10 @@ struct gk20a {
         struct pmu_gk20a pmu;
         struct acr_desc acr;
         struct cooling_device_gk20a gk20a_cdev;
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+        struct clk_pmupstate clk_pmu;
+        struct perf_pmupstate perf_pmu;
+#endif
 
 #ifdef CONFIG_DEBUG_FS
         struct railgate_stats pstats;
@@ -992,6 +1003,7 @@ enum gk20a_dbg_categories {
         gpu_dbg_map_v   = BIT(14), /* verbose mem mappings */
         gpu_dbg_sema    = BIT(15), /* semaphore debugging */
         gpu_dbg_sema_v  = BIT(16), /* verbose semaphore debugging */
+        gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */
         gpu_dbg_mem     = BIT(31), /* memory accesses, very verbose */
 };
 
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
index 550dffa6..b1e94d7d 100644
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
@@ -142,6 +142,7 @@ int gk20a_init_hal(struct gk20a *g)
         *gops = gk20a_ops;
         gops->privsecurity = 0;
         gops->securegpccs = 0;
+        gops->pmupstate = false;
         gk20a_init_mc(gops);
         gk20a_init_ltc(gops);
         gk20a_init_gr_ops(gops);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
index aa10661c..d256f6d2 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_api.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -458,6 +458,29 @@ enum {
         PMU_PG_ELPG_CMD_UNFREEZE,
 };
 
+enum {
+        PMU_PG_CMD_ID_ELPG_CMD = 0,
+        PMU_PG_CMD_ID_ENG_BUF_LOAD,
+        PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
+        PMU_PG_CMD_ID_PG_STAT,
+        PMU_PG_CMD_ID_PG_LOG_INIT,
+        PMU_PG_CMD_ID_PG_LOG_FLUSH,
+        PMU_PG_CMD_ID_PG_PARAM,
+        PMU_PG_CMD_ID_ELPG_INIT,
+        PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
+        PMU_PG_CMD_ID_ELPG_ABORT_POLL,
+        PMU_PG_CMD_ID_ELPG_PWR_UP,
+        PMU_PG_CMD_ID_ELPG_DISALLOW,
+        PMU_PG_CMD_ID_ELPG_ALLOW,
+        PMU_PG_CMD_ID_AP,
+        RM_PMU_PG_CMD_ID_PSI,
+        RM_PMU_PG_CMD_ID_CG,
+        PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
+        PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
+        PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
+        PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE
+};
+
 struct pmu_pg_cmd_elpg_cmd {
         u8 cmd_type;
         u8 engine_id;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h
index 76b37cf7..de37caeb 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_common.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_common.h
@@ -95,6 +95,8 @@ struct flcn_u64 {
         u32 hi;
 };
 
+#define nv_flcn_u64 flcn_u64
+
 struct flcn_mem_desc_v0 {
         struct flcn_u64 address;
         u32 params;
@@ -132,6 +134,8 @@ struct pmu_allocation_v3 {
         } alloc;
 };
 
+#define nv_pmu_allocation pmu_allocation_v3
+
 struct pmu_hdr {
         u8 unit_id;
         u8 size;
@@ -142,4 +146,36 @@ struct pmu_hdr {
 #define nv_pmu_hdr pmu_hdr
 typedef u8 flcn_status;
 
-#endif /*__PMU_COMMON_H__*/
+#define ALIGN_UP(v, gran)       (((v) + ((gran) - 1)) & ~((gran)-1))
+
+/*!
+ * Falcon PMU DMA's minimum size in bytes.
+ */
+#define PMU_DMA_MIN_READ_SIZE_BYTES                                    16
+#define PMU_DMA_MIN_WRITE_SIZE_BYTES                                      4
+
+#define PMU_FB_COPY_RW_ALIGNMENT                                          \
+        (PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES ?     \
+        PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
+
+/*!
+ * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
+ * data structures to issue DMA read/write operations.
+ */
+#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size)           \
+union name##_aligned {                                   \
+                struct name data;                        \
+                u8 pad[ALIGN_UP(sizeof(struct name),     \
+                (PMU_FB_COPY_RW_ALIGNMENT))];            \
+}
+
+#define NV_PMU_MAKE_ALIGNED_UNION(name, size)            \
+union name##_aligned {                                   \
+                union name data;                         \
+                u8 pad[ALIGN_UP(sizeof(union name),      \
+                (PMU_FB_COPY_RW_ALIGNMENT))];            \
+}
+
+#define NV_UNSIGNED_ROUNDED_DIV(a, b)    (((a) + ((b) / 2)) / (b))
+
+#endif
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index f041c9c1..13d3ec78 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -3756,9 +3756,6 @@ static int pmu_response_handle(struct pmu_gk20a *pmu,
                 }
                 if (pv->pmu_allocation_get_dmem_size(pmu,
                 pv->get_pmu_seq_out_a_ptr(seq)) != 0) {
-                  gk20a_err(dev_from_gk20a(g), "dmem offs %x size %x\n", pv->pmu_allocation_get_dmem_offset(pmu,pv->get_pmu_seq_out_a_ptr(seq)), pv->pmu_allocation_get_dmem_size(pmu,
-pv->get_pmu_seq_out_a_ptr(seq)));
-                  gk20a_err(dev_from_gk20a(g), "copying to %p \n", seq->out_payload);
                         pmu_copy_from_dmem(pmu,
                         pv->pmu_allocation_get_dmem_offset(pmu,
                         pv->get_pmu_seq_out_a_ptr(seq)),
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index f0e5d3cf..fd27ab5c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -23,6 +23,9 @@
 
 #include "pmu_api.h"
 #include "pmu_common.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "pmuif/gpmuifperf.h"
 
 /* defined by pmu hw spec */
 #define GK20A_PMU_VA_SIZE               (512 * 1024 * 1024)
@@ -172,8 +175,10 @@ struct pmu_ucode_desc_v1 {
 #define PMU_UNIT_ACR            (0x0A)
 #define PMU_UNIT_PERFMON_T18X   (0x11)
 #define PMU_UNIT_PERFMON        (0x12)
-#define PMU_UNIT_RC                     (0x1F)
+#define PMU_UNIT_PERF            (0x13)
+#define PMU_UNIT_RC             (0x1F)
 #define PMU_UNIT_FECS_MEM_OVERRIDE      (0x1E)
+#define PMU_UNIT_CLK             (0x1C)
 
 #define PMU_UNIT_END            (0x23)
 
@@ -295,29 +300,6 @@ struct pmu_rc_msg {
         struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
 };
 
-enum {
-        PMU_PG_CMD_ID_ELPG_CMD = 0,
-        PMU_PG_CMD_ID_ENG_BUF_LOAD,
-        PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
-        PMU_PG_CMD_ID_PG_STAT,
-        PMU_PG_CMD_ID_PG_LOG_INIT,
-        PMU_PG_CMD_ID_PG_LOG_FLUSH,
-        PMU_PG_CMD_ID_PG_PARAM,
-        PMU_PG_CMD_ID_ELPG_INIT,
-        PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
-        PMU_PG_CMD_ID_ELPG_ABORT_POLL,
-        PMU_PG_CMD_ID_ELPG_PWR_UP,
-        PMU_PG_CMD_ID_ELPG_DISALLOW,
-        PMU_PG_CMD_ID_ELPG_ALLOW,
-        PMU_PG_CMD_ID_AP,
-        RM_PMU_PG_CMD_ID_PSI,
-        RM_PMU_PG_CMD_ID_CG,
-        PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
-        PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
-        PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
-        PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE
-};
-
 /***************************** ACR ERROR CODES  ******************************/
 /*!
  * Error codes used in PMU-ACR Task
@@ -369,6 +351,9 @@ struct pmu_cmd {
                 struct pmu_zbc_cmd zbc;
                 struct pmu_acr_cmd acr;
                 struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram;
+                struct nv_pmu_boardobj_cmd boardobj;
+                struct nv_pmu_perf_cmd perf;
+                struct nv_pmu_clk_cmd clk;
         } cmd;
 };
 
@@ -381,6 +366,9 @@ struct pmu_msg {
                 struct pmu_rc_msg rc;
                 struct pmu_acr_msg acr;
                 struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram;
+                struct nv_pmu_boardobj_msg boardobj;
+                struct nv_pmu_perf_msg perf;
+                struct nv_pmu_clk_msg clk;
         } msg;
 };
 
@@ -813,4 +801,6 @@ int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem,
                 u32 size);
 int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem,
                 u32 size);
+
+void print_vbios_table(u8 *msg, u8 *buff, int size);
 #endif /*__PMU_GK20A_H__*/