diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.h | 5 |
5 files changed, 17 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c98fec48..03510a16 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1133,7 +1133,8 @@ struct gpu_ops { | |||
1133 | struct { | 1133 | struct { |
1134 | int (*exec_regops)(struct dbg_session_gk20a *dbg_s, | 1134 | int (*exec_regops)(struct dbg_session_gk20a *dbg_s, |
1135 | struct nvgpu_dbg_reg_op *ops, | 1135 | struct nvgpu_dbg_reg_op *ops, |
1136 | u64 num_ops); | 1136 | u64 num_ops, |
1137 | bool *is_current_ctx); | ||
1137 | const struct regop_offset_range* ( | 1138 | const struct regop_offset_range* ( |
1138 | *get_global_whitelist_ranges)(void); | 1139 | *get_global_whitelist_ranges)(void); |
1139 | u64 (*get_global_whitelist_ranges_count)(void); | 1140 | u64 (*get_global_whitelist_ranges_count)(void); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index a40d93fd..f3b580e4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
8358 | 8358 | ||
8359 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 8359 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
8360 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, | 8360 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
8361 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) | 8361 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, |
8362 | bool *is_curr_ctx) | ||
8362 | { | 8363 | { |
8363 | struct gk20a *g = ch->g; | 8364 | struct gk20a *g = ch->g; |
8364 | int err, tmp_err; | 8365 | int err, tmp_err; |
@@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
8376 | } | 8377 | } |
8377 | 8378 | ||
8378 | ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch); | 8379 | ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch); |
8379 | 8380 | if (is_curr_ctx != NULL) { | |
8381 | *is_curr_ctx = ch_is_curr_ctx; | ||
8382 | } | ||
8380 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d", | 8383 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d", |
8381 | ch_is_curr_ctx); | 8384 | ch_is_curr_ctx); |
8382 | 8385 | ||
@@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g, | |||
8694 | i++; | 8697 | i++; |
8695 | } | 8698 | } |
8696 | 8699 | ||
8697 | err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); | 8700 | err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL); |
8698 | if (err) { | 8701 | if (err) { |
8699 | nvgpu_err(g, "Failed to access register"); | 8702 | nvgpu_err(g, "Failed to access register"); |
8700 | } | 8703 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 4f83bba3..617aad34 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -616,7 +616,8 @@ int gk20a_gr_suspend(struct gk20a *g); | |||
616 | struct nvgpu_dbg_reg_op; | 616 | struct nvgpu_dbg_reg_op; |
617 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 617 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
618 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, | 618 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
619 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); | 619 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, |
620 | bool *is_curr_ctx); | ||
620 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 621 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
621 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, | 622 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
622 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, | 623 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 80d27c25..0aec4f86 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -89,7 +89,8 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
89 | 89 | ||
90 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | 90 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, |
91 | struct nvgpu_dbg_reg_op *ops, | 91 | struct nvgpu_dbg_reg_op *ops, |
92 | u64 num_ops) | 92 | u64 num_ops, |
93 | bool *is_current_ctx) | ||
93 | { | 94 | { |
94 | int err = 0; | 95 | int err = 0; |
95 | unsigned int i; | 96 | unsigned int i; |
@@ -219,7 +220,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
219 | 220 | ||
220 | if (ctx_wr_count | ctx_rd_count) { | 221 | if (ctx_wr_count | ctx_rd_count) { |
221 | err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops, | 222 | err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops, |
222 | ctx_wr_count, ctx_rd_count); | 223 | ctx_wr_count, ctx_rd_count, |
224 | is_current_ctx); | ||
223 | if (err) { | 225 | if (err) { |
224 | nvgpu_warn(g, "failed to perform ctx ops\n"); | 226 | nvgpu_warn(g, "failed to perform ctx ops\n"); |
225 | goto clean_up; | 227 | goto clean_up; |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h index 0fb108a4..96705879 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -77,7 +77,8 @@ struct regop_offset_range { | |||
77 | 77 | ||
78 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | 78 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, |
79 | struct nvgpu_dbg_reg_op *ops, | 79 | struct nvgpu_dbg_reg_op *ops, |
80 | u64 num_ops); | 80 | u64 num_ops, |
81 | bool *is_current_ctx); | ||
81 | 82 | ||
82 | /* turn seriously unwieldy names -> something shorter */ | 83 | /* turn seriously unwieldy names -> something shorter */ |
83 | #define REGOP(x) NVGPU_DBG_REG_OP_##x | 84 | #define REGOP(x) NVGPU_DBG_REG_OP_##x |