diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 51 |
1 files changed, 32 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 09e8aa0f..6abc7d41 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2149,12 +2149,40 @@ clean_up: | |||
2149 | return err; | 2149 | return err; |
2150 | } | 2150 | } |
2151 | 2151 | ||
2152 | static void gr_gk20a_wait_for_fecs_arb_idle(struct gk20a *g) | ||
2153 | { | ||
2154 | int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | ||
2155 | u32 val; | ||
2156 | |||
2157 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | ||
2158 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | ||
2159 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | ||
2160 | retries--; | ||
2161 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | ||
2162 | } | ||
2163 | |||
2164 | if (!retries) | ||
2165 | nvgpu_err(g, "arbiter cmd timeout, fecs arb ctx cmd: 0x%08x", | ||
2166 | gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); | ||
2167 | |||
2168 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | ||
2169 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & | ||
2170 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { | ||
2171 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | ||
2172 | retries--; | ||
2173 | } | ||
2174 | if (!retries) { | ||
2175 | nvgpu_err(g, | ||
2176 | "arbiter idle timeout, fecs ctxsw status: 0x%08x", | ||
2177 | gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); | ||
2178 | } | ||
2179 | } | ||
2180 | |||
2152 | void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | 2181 | void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) |
2153 | { | 2182 | { |
2154 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; | 2183 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; |
2155 | int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | 2184 | int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2156 | u64 inst_ptr; | 2185 | u64 inst_ptr; |
2157 | u32 val; | ||
2158 | 2186 | ||
2159 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & | 2187 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & |
2160 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { | 2188 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { |
@@ -2186,15 +2214,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2186 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); | 2214 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); |
2187 | 2215 | ||
2188 | /* Wait for arbiter command to complete */ | 2216 | /* Wait for arbiter command to complete */ |
2189 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | 2217 | gr_gk20a_wait_for_fecs_arb_idle(g); |
2190 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | ||
2191 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | ||
2192 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | ||
2193 | retries--; | ||
2194 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | ||
2195 | } | ||
2196 | if (!retries) | ||
2197 | nvgpu_err(g, "arbiter complete timeout"); | ||
2198 | 2218 | ||
2199 | gk20a_writel(g, gr_fecs_current_ctx_r(), | 2219 | gk20a_writel(g, gr_fecs_current_ctx_r(), |
2200 | gr_fecs_current_ctx_ptr_f(inst_ptr >> 12) | | 2220 | gr_fecs_current_ctx_ptr_f(inst_ptr >> 12) | |
@@ -2203,15 +2223,8 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2203 | /* Send command to arbiter to flush */ | 2223 | /* Send command to arbiter to flush */ |
2204 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), gr_fecs_arb_ctx_cmd_cmd_s()); | 2224 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), gr_fecs_arb_ctx_cmd_cmd_s()); |
2205 | 2225 | ||
2206 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | 2226 | gr_gk20a_wait_for_fecs_arb_idle(g); |
2207 | val = (gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); | 2227 | |
2208 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | ||
2209 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | ||
2210 | retries--; | ||
2211 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | ||
2212 | } | ||
2213 | if (!retries) | ||
2214 | nvgpu_err(g, "arbiter complete timeout"); | ||
2215 | } | 2228 | } |
2216 | 2229 | ||
2217 | void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base, | 2230 | void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base, |