diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 44 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 |
2 files changed, 27 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index b2800772..60481544 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -65,7 +65,7 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
65 | 65 | ||
66 | void gk20a_bus_isr(struct gk20a *g) | 66 | void gk20a_bus_isr(struct gk20a *g) |
67 | { | 67 | { |
68 | u32 val, save0, save1, err_code; | 68 | u32 val, save0, save1, fecs_errcode = 0; |
69 | 69 | ||
70 | val = gk20a_readl(g, bus_intr_0_r()); | 70 | val = gk20a_readl(g, bus_intr_0_r()); |
71 | 71 | ||
@@ -78,29 +78,37 @@ void gk20a_bus_isr(struct gk20a *g) | |||
78 | 78 | ||
79 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); | 79 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); |
80 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { | 80 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { |
81 | 81 | /* | |
82 | err_code = gk20a_readl(g, | 82 | * write & addr fields in timeout_save0 |
83 | * might not be reliable | ||
84 | */ | ||
85 | fecs_errcode = gk20a_readl(g, | ||
83 | timer_pri_timeout_fecs_errcode_r()); | 86 | timer_pri_timeout_fecs_errcode_r()); |
84 | /* write and addr fields are not reliable */ | 87 | } |
85 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x " | 88 | |
86 | "FECS_ERRCODE 0x%08x", val, err_code); | 89 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); |
90 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
91 | "%s DATA 0x%08x ", | ||
92 | val, | ||
93 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
94 | timer_pri_timeout_save_0_write_v(save0) ? | ||
95 | "WRITE" : "READ", save1); | ||
87 | 96 | ||
88 | if ((err_code & 0xffffff00) == 0xbadf1300) | 97 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); |
98 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | ||
99 | |||
100 | if (fecs_errcode) { | ||
101 | nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); | ||
102 | if (g->ops.priv_ring.decode_error_code) | ||
103 | g->ops.priv_ring.decode_error_code(g, | ||
104 | fecs_errcode); | ||
105 | |||
106 | if ((fecs_errcode & 0xffffff00) == 0xbadf1300) | ||
89 | nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " | 107 | nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " |
90 | "0x%08x", | 108 | "0x%08x", |
91 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); | 109 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); |
92 | } else { | ||
93 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); | ||
94 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
95 | "R/W %s DATA 0x%08x", | ||
96 | val, | ||
97 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
98 | timer_pri_timeout_save_0_write_v(save0) ? | ||
99 | "WRITE" : "READ", save1); | ||
100 | } | 110 | } |
101 | 111 | ||
102 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); | ||
103 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | ||
104 | } else { | 112 | } else { |
105 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); | 113 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); |
106 | } | 114 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 95736d30..7162dc73 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1113,6 +1113,7 @@ struct gpu_ops { | |||
1113 | } falcon; | 1113 | } falcon; |
1114 | struct { | 1114 | struct { |
1115 | void (*isr)(struct gk20a *g); | 1115 | void (*isr)(struct gk20a *g); |
1116 | void (*decode_error_code)(struct gk20a *g, u32 error_code); | ||
1116 | } priv_ring; | 1117 | } priv_ring; |
1117 | struct { | 1118 | struct { |
1118 | int (*check_priv_security)(struct gk20a *g); | 1119 | int (*check_priv_security)(struct gk20a *g); |