diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 2 |
6 files changed, 38 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h index f04ff56c..0d1ed5df 100644 --- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | |||
@@ -32,9 +32,6 @@ struct gk20a_ecc_stat { | |||
32 | #endif | 32 | #endif |
33 | }; | 33 | }; |
34 | 34 | ||
35 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
36 | #include "ecc_t18x.h" | ||
37 | #endif | ||
38 | #ifdef CONFIG_TEGRA_19x_GPU | 35 | #ifdef CONFIG_TEGRA_19x_GPU |
39 | #include "ecc_t19x.h" | 36 | #include "ecc_t19x.h" |
40 | #endif | 37 | #endif |
@@ -42,15 +39,30 @@ struct gk20a_ecc_stat { | |||
42 | struct ecc_gk20a { | 39 | struct ecc_gk20a { |
43 | /* Stats per engine */ | 40 | /* Stats per engine */ |
44 | struct { | 41 | struct { |
45 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 42 | struct gk20a_ecc_stat sm_lrf_single_err_count; |
46 | struct ecc_gr_t18x t18x; | 43 | struct gk20a_ecc_stat sm_lrf_double_err_count; |
47 | #endif | 44 | |
45 | struct gk20a_ecc_stat sm_shm_sec_count; | ||
46 | struct gk20a_ecc_stat sm_shm_sed_count; | ||
47 | struct gk20a_ecc_stat sm_shm_ded_count; | ||
48 | |||
49 | struct gk20a_ecc_stat tex_total_sec_pipe0_count; | ||
50 | struct gk20a_ecc_stat tex_total_ded_pipe0_count; | ||
51 | struct gk20a_ecc_stat tex_unique_sec_pipe0_count; | ||
52 | struct gk20a_ecc_stat tex_unique_ded_pipe0_count; | ||
53 | struct gk20a_ecc_stat tex_total_sec_pipe1_count; | ||
54 | struct gk20a_ecc_stat tex_total_ded_pipe1_count; | ||
55 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | ||
56 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | ||
57 | |||
48 | #ifdef CONFIG_TEGRA_19x_GPU | 58 | #ifdef CONFIG_TEGRA_19x_GPU |
49 | struct ecc_gr_t19x t19x; | 59 | struct ecc_gr_t19x t19x; |
50 | #endif | 60 | #endif |
51 | } gr; | 61 | } gr; |
52 | 62 | ||
53 | struct { | 63 | struct { |
64 | struct gk20a_ecc_stat l2_sec_count; | ||
65 | struct gk20a_ecc_stat l2_ded_count; | ||
54 | #ifdef CONFIG_TEGRA_19x_GPU | 66 | #ifdef CONFIG_TEGRA_19x_GPU |
55 | struct ecc_ltc_t19x t19x; | 67 | struct ecc_ltc_t19x t19x; |
56 | #endif | 68 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 5bdd81ac..c029e9e0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -46,9 +46,7 @@ | |||
46 | #include "mc_gk20a.h" | 46 | #include "mc_gk20a.h" |
47 | #include "hal.h" | 47 | #include "hal.h" |
48 | #include "bus_gk20a.h" | 48 | #include "bus_gk20a.h" |
49 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
50 | #include "pstate/pstate.h" | 49 | #include "pstate/pstate.h" |
51 | #endif | ||
52 | 50 | ||
53 | #ifdef CONFIG_TEGRA_19x_GPU | 51 | #ifdef CONFIG_TEGRA_19x_GPU |
54 | #include "nvgpu_gpuid_t19x.h" | 52 | #include "nvgpu_gpuid_t19x.h" |
@@ -112,10 +110,9 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
112 | if (g->ops.clk.suspend_clk_support) | 110 | if (g->ops.clk.suspend_clk_support) |
113 | ret |= g->ops.clk.suspend_clk_support(g); | 111 | ret |= g->ops.clk.suspend_clk_support(g); |
114 | 112 | ||
115 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
116 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) | 113 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) |
117 | gk20a_deinit_pstate_support(g); | 114 | gk20a_deinit_pstate_support(g); |
118 | #endif | 115 | |
119 | g->power_on = false; | 116 | g->power_on = false; |
120 | 117 | ||
121 | return ret; | 118 | return ret; |
@@ -240,7 +237,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
240 | } | 237 | } |
241 | } | 238 | } |
242 | 239 | ||
243 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
244 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { | 240 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { |
245 | err = gk20a_init_pstate_support(g); | 241 | err = gk20a_init_pstate_support(g); |
246 | if (err) { | 242 | if (err) { |
@@ -248,7 +244,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
248 | goto done; | 244 | goto done; |
249 | } | 245 | } |
250 | } | 246 | } |
251 | #endif | ||
252 | 247 | ||
253 | if (g->ops.pmu.is_pmu_supported(g)) { | 248 | if (g->ops.pmu.is_pmu_supported(g)) { |
254 | err = nvgpu_init_pmu_support(g); | 249 | err = nvgpu_init_pmu_support(g); |
@@ -264,7 +259,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
264 | goto done; | 259 | goto done; |
265 | } | 260 | } |
266 | 261 | ||
267 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
268 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { | 262 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { |
269 | err = gk20a_init_pstate_pmu_support(g); | 263 | err = gk20a_init_pstate_pmu_support(g); |
270 | if (err) { | 264 | if (err) { |
@@ -278,7 +272,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
278 | nvgpu_err(g, "failed to init clk arb"); | 272 | nvgpu_err(g, "failed to init clk arb"); |
279 | goto done; | 273 | goto done; |
280 | } | 274 | } |
281 | #endif | ||
282 | 275 | ||
283 | err = gk20a_init_therm_support(g); | 276 | err = gk20a_init_therm_support(g); |
284 | if (err) { | 277 | if (err) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fef9f498..8d8bfbec 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -72,12 +72,10 @@ struct nvgpu_ctxsw_trace_filter; | |||
72 | #include "pmu_gk20a.h" | 72 | #include "pmu_gk20a.h" |
73 | #include "priv_ring_gk20a.h" | 73 | #include "priv_ring_gk20a.h" |
74 | #include "therm_gk20a.h" | 74 | #include "therm_gk20a.h" |
75 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
76 | #include "clk/clk.h" | 75 | #include "clk/clk.h" |
77 | #include "perf/perf.h" | 76 | #include "perf/perf.h" |
78 | #include "pmgr/pmgr.h" | 77 | #include "pmgr/pmgr.h" |
79 | #include "therm/thrm.h" | 78 | #include "therm/thrm.h" |
80 | #endif | ||
81 | #include "ecc_gk20a.h" | 79 | #include "ecc_gk20a.h" |
82 | 80 | ||
83 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | 81 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. |
@@ -1128,12 +1126,10 @@ struct gk20a { | |||
1128 | struct nvgpu_pmu pmu; | 1126 | struct nvgpu_pmu pmu; |
1129 | struct acr_desc acr; | 1127 | struct acr_desc acr; |
1130 | struct ecc_gk20a ecc; | 1128 | struct ecc_gk20a ecc; |
1131 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
1132 | struct clk_pmupstate clk_pmu; | 1129 | struct clk_pmupstate clk_pmu; |
1133 | struct perf_pmupstate perf_pmu; | 1130 | struct perf_pmupstate perf_pmu; |
1134 | struct pmgr_pmupstate pmgr_pmu; | 1131 | struct pmgr_pmupstate pmgr_pmu; |
1135 | struct therm_pmupstate therm_pmu; | 1132 | struct therm_pmupstate therm_pmu; |
1136 | #endif | ||
1137 | 1133 | ||
1138 | #ifdef CONFIG_DEBUG_FS | 1134 | #ifdef CONFIG_DEBUG_FS |
1139 | struct railgate_stats pstats; | 1135 | struct railgate_stats pstats; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index f44e96a7..0df88988 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -24,9 +24,6 @@ | |||
24 | #ifndef GR_GK20A_H | 24 | #ifndef GR_GK20A_H |
25 | #define GR_GK20A_H | 25 | #define GR_GK20A_H |
26 | 26 | ||
27 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
28 | #include "gr_t18x.h" | ||
29 | #endif | ||
30 | #ifdef CONFIG_TEGRA_19x_GPU | 27 | #ifdef CONFIG_TEGRA_19x_GPU |
31 | #include "gr_t19x.h" | 28 | #include "gr_t19x.h" |
32 | #endif | 29 | #endif |
@@ -316,6 +313,11 @@ struct gr_gk20a { | |||
316 | } ctxsw_regs; | 313 | } ctxsw_regs; |
317 | int regs_base_index; | 314 | int regs_base_index; |
318 | bool valid; | 315 | bool valid; |
316 | |||
317 | u32 preempt_image_size; | ||
318 | bool force_preemption_gfxp; | ||
319 | bool force_preemption_cilp; | ||
320 | bool dump_ctxsw_stats_on_channel_close; | ||
319 | } ctx_vars; | 321 | } ctx_vars; |
320 | 322 | ||
321 | struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */ | 323 | struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */ |
@@ -409,9 +411,11 @@ struct gr_gk20a { | |||
409 | bool sw_ready; | 411 | bool sw_ready; |
410 | bool skip_ucode_init; | 412 | bool skip_ucode_init; |
411 | 413 | ||
412 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 414 | struct nvgpu_preemption_modes_rec preemption_mode_rec; |
413 | struct gr_t18x t18x; | 415 | |
414 | #endif | 416 | u32 fecs_feature_override_ecc_val; |
417 | |||
418 | int cilp_preempt_pending_chid; | ||
415 | 419 | ||
416 | u32 fbp_en_mask; | 420 | u32 fbp_en_mask; |
417 | u32 *fbp_rop_l2_en_mask; | 421 | u32 *fbp_rop_l2_en_mask; |
@@ -433,9 +437,15 @@ struct gr_ctx_desc { | |||
433 | u32 graphics_preempt_mode; | 437 | u32 graphics_preempt_mode; |
434 | u32 compute_preempt_mode; | 438 | u32 compute_preempt_mode; |
435 | bool boosted_ctx; | 439 | bool boosted_ctx; |
436 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 440 | |
437 | struct gr_ctx_desc_t18x t18x; | 441 | struct nvgpu_mem preempt_ctxsw_buffer; |
438 | #endif | 442 | struct nvgpu_mem spill_ctxsw_buffer; |
443 | struct nvgpu_mem betacb_ctxsw_buffer; | ||
444 | struct nvgpu_mem pagepool_ctxsw_buffer; | ||
445 | u32 ctx_id; | ||
446 | bool ctx_id_valid; | ||
447 | bool cilp_preempt_pending; | ||
448 | |||
439 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 449 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
440 | u64 virt_ctx; | 450 | u64 virt_ctx; |
441 | #endif | 451 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c index 13e6f374..d24d4bc5 100644 --- a/drivers/gpu/nvgpu/gk20a/hal.c +++ b/drivers/gpu/nvgpu/gk20a/hal.c | |||
@@ -44,7 +44,6 @@ int gpu_init_hal(struct gk20a *g) | |||
44 | if (gm20b_init_hal(g)) | 44 | if (gm20b_init_hal(g)) |
45 | return -ENODEV; | 45 | return -ENODEV; |
46 | break; | 46 | break; |
47 | #if defined(CONFIG_ARCH_TEGRA_18x_SOC) | ||
48 | case NVGPU_GPUID_GP10B: | 47 | case NVGPU_GPUID_GP10B: |
49 | if (gp10b_init_hal(g)) | 48 | if (gp10b_init_hal(g)) |
50 | return -ENODEV; | 49 | return -ENODEV; |
@@ -54,7 +53,6 @@ int gpu_init_hal(struct gk20a *g) | |||
54 | if (gp106_init_hal(g)) | 53 | if (gp106_init_hal(g)) |
55 | return -ENODEV; | 54 | return -ENODEV; |
56 | break; | 55 | break; |
57 | #endif | ||
58 | #ifdef CONFIG_TEGRA_19x_GPU | 56 | #ifdef CONFIG_TEGRA_19x_GPU |
59 | case TEGRA_19x_GPUID: | 57 | case TEGRA_19x_GPUID: |
60 | if (TEGRA_19x_GPUID_HAL(g)) | 58 | if (TEGRA_19x_GPUID_HAL(g)) |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index d8478b2d..4e3eeb51 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -589,12 +589,10 @@ int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu, | |||
589 | 589 | ||
590 | switch (msg->msg_type) { | 590 | switch (msg->msg_type) { |
591 | case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION: | 591 | case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION: |
592 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
593 | if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1)) | 592 | if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1)) |
594 | nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu), | 593 | nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu), |
595 | (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD)); | 594 | (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD)); |
596 | else | 595 | else |
597 | #endif | ||
598 | gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d", | 596 | gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d", |
599 | msg->hw_slct_msg.mask); | 597 | msg->hw_slct_msg.mask); |
600 | break; | 598 | break; |