diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 23 |
6 files changed, 35 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 731074de..034d060a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -590,14 +590,16 @@ static int gk20a_init_fifo_setup_hw(struct gk20a *g) | |||
590 | smp_mb(); | 590 | smp_mb(); |
591 | 591 | ||
592 | if (v1 != gk20a_bar1_readl(g, bar1_vaddr)) { | 592 | if (v1 != gk20a_bar1_readl(g, bar1_vaddr)) { |
593 | gk20a_err(dev_from_gk20a(g), "bar1 broken @ gk20a!"); | 593 | gk20a_err(dev_from_gk20a(g), "bar1 broken @ gk20a: CPU wrote 0x%x, \ |
594 | GPU read 0x%x", *cpu_vaddr, gk20a_bar1_readl(g, bar1_vaddr)); | ||
594 | return -EINVAL; | 595 | return -EINVAL; |
595 | } | 596 | } |
596 | 597 | ||
597 | gk20a_bar1_writel(g, bar1_vaddr, v2); | 598 | gk20a_bar1_writel(g, bar1_vaddr, v2); |
598 | 599 | ||
599 | if (v2 != gk20a_bar1_readl(g, bar1_vaddr)) { | 600 | if (v2 != gk20a_bar1_readl(g, bar1_vaddr)) { |
600 | gk20a_err(dev_from_gk20a(g), "bar1 broken @ gk20a!"); | 601 | gk20a_err(dev_from_gk20a(g), "bar1 broken @ gk20a: GPU wrote 0x%x, \ |
602 | CPU read 0x%x", gk20a_bar1_readl(g, bar1_vaddr), *cpu_vaddr); | ||
601 | return -EINVAL; | 603 | return -EINVAL; |
602 | } | 604 | } |
603 | 605 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d8e3586f..9a183e44 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -333,6 +333,7 @@ struct gpu_ops { | |||
333 | struct { | 333 | struct { |
334 | int (*get_netlist_name)(int index, char *name); | 334 | int (*get_netlist_name)(int index, char *name); |
335 | bool (*is_fw_defined)(void); | 335 | bool (*is_fw_defined)(void); |
336 | bool use_dma_for_fw_bootstrap; | ||
336 | } gr_ctx; | 337 | } gr_ctx; |
337 | struct { | 338 | struct { |
338 | bool (*support_sparse)(struct gk20a *g); | 339 | bool (*support_sparse)(struct gk20a *g); |
@@ -383,7 +384,9 @@ struct gpu_ops { | |||
383 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); | 384 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); |
384 | int (*pmu_setup_elpg)(struct gk20a *g); | 385 | int (*pmu_setup_elpg)(struct gk20a *g); |
385 | int (*init_wpr_region)(struct gk20a *g); | 386 | int (*init_wpr_region)(struct gk20a *g); |
387 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); | ||
386 | u32 lspmuwprinitdone; | 388 | u32 lspmuwprinitdone; |
389 | u32 lsfloadedfalconid; | ||
387 | bool fecsbootstrapdone; | 390 | bool fecsbootstrapdone; |
388 | } pmu; | 391 | } pmu; |
389 | struct { | 392 | struct { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index cd9a9fca..94dba7b6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A Graphics Context | 4 | * GK20A Graphics Context |
5 | * | 5 | * |
6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -345,4 +345,5 @@ void gk20a_init_gr_ctx(struct gpu_ops *gops) | |||
345 | { | 345 | { |
346 | gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name; | 346 | gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name; |
347 | gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined; | 347 | gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined; |
348 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
348 | } | 349 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index edd4c6c8..e232bf17 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2128,7 +2128,7 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | |||
2128 | * In case bootloader is not supported, revert to the old way of | 2128 | * In case bootloader is not supported, revert to the old way of |
2129 | * loading gr ucode, without the faster bootstrap routine. | 2129 | * loading gr ucode, without the faster bootstrap routine. |
2130 | */ | 2130 | */ |
2131 | if (g->gpu_characteristics.arch > NVGPU_GPU_ARCH_GM200) { | 2131 | if (!g->ops.gr_ctx.use_dma_for_fw_bootstrap) { |
2132 | gr_gk20a_load_falcon_dmem(g); | 2132 | gr_gk20a_load_falcon_dmem(g); |
2133 | gr_gk20a_load_falcon_imem(g); | 2133 | gr_gk20a_load_falcon_imem(g); |
2134 | gr_gk20a_start_falcon_ucode(g); | 2134 | gr_gk20a_start_falcon_ucode(g); |
@@ -2161,7 +2161,7 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) | |||
2161 | return ret; | 2161 | return ret; |
2162 | } | 2162 | } |
2163 | 2163 | ||
2164 | if (!(g->gpu_characteristics.arch > NVGPU_GPU_ARCH_GM200)) | 2164 | if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || g->ops.securegpccs) |
2165 | gk20a_writel(g, gr_fecs_current_ctx_r(), | 2165 | gk20a_writel(g, gr_fecs_current_ctx_r(), |
2166 | gr_fecs_current_ctx_valid_false_f()); | 2166 | gr_fecs_current_ctx_valid_false_f()); |
2167 | 2167 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 11322293..1f21555c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2647,6 +2647,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2647 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; | 2647 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; |
2648 | gops->pmu.pmu_setup_elpg = NULL; | 2648 | gops->pmu.pmu_setup_elpg = NULL; |
2649 | gops->pmu.init_wpr_region = NULL; | 2649 | gops->pmu.init_wpr_region = NULL; |
2650 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
2650 | } | 2651 | } |
2651 | 2652 | ||
2652 | int gk20a_init_pmu_support(struct gk20a *g) | 2653 | int gk20a_init_pmu_support(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index f29c810e..85403767 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -304,6 +304,11 @@ enum { | |||
304 | GK20A_PMU_DMAIDX_END = 7 | 304 | GK20A_PMU_DMAIDX_END = 7 |
305 | }; | 305 | }; |
306 | 306 | ||
307 | struct falc_u64 { | ||
308 | u32 lo; | ||
309 | u32 hi; | ||
310 | }; | ||
311 | |||
307 | struct falc_dma_addr { | 312 | struct falc_dma_addr { |
308 | u32 dma_base; | 313 | u32 dma_base; |
309 | /*dma_base1 is 9-bit MSB for FB Base | 314 | /*dma_base1 is 9-bit MSB for FB Base |
@@ -708,6 +713,8 @@ struct pmu_pg_cmd { | |||
708 | enum { | 713 | enum { |
709 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 , | 714 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 , |
710 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, | 715 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, |
716 | PMU_ACR_CMD_ID_RESERVED, | ||
717 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, | ||
711 | }; | 718 | }; |
712 | 719 | ||
713 | /* | 720 | /* |
@@ -729,14 +736,27 @@ struct pmu_acr_cmd_bootstrap_falcon { | |||
729 | u32 falconid; | 736 | u32 falconid; |
730 | }; | 737 | }; |
731 | 738 | ||
739 | /* | ||
740 | * falcon ID to bootstrap | ||
741 | */ | ||
742 | struct pmu_acr_cmd_bootstrap_multiple_falcons { | ||
743 | u8 cmd_type; | ||
744 | u32 flags; | ||
745 | u32 falconidmask; | ||
746 | u32 usevamask; | ||
747 | struct falc_u64 wprvirtualbase; | ||
748 | }; | ||
749 | |||
732 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 | 750 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 |
733 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 | 751 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 |
734 | 752 | ||
753 | |||
735 | struct pmu_acr_cmd { | 754 | struct pmu_acr_cmd { |
736 | union { | 755 | union { |
737 | u8 cmd_type; | 756 | u8 cmd_type; |
738 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; | 757 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; |
739 | struct pmu_acr_cmd_init_wpr_details init_wpr; | 758 | struct pmu_acr_cmd_init_wpr_details init_wpr; |
759 | struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; | ||
740 | }; | 760 | }; |
741 | }; | 761 | }; |
742 | 762 | ||
@@ -1177,6 +1197,7 @@ struct pmu_gk20a { | |||
1177 | /* TBD: remove this if ZBC seq is fixed */ | 1197 | /* TBD: remove this if ZBC seq is fixed */ |
1178 | struct mem_desc seq_buf; | 1198 | struct mem_desc seq_buf; |
1179 | struct mem_desc trace_buf; | 1199 | struct mem_desc trace_buf; |
1200 | struct mem_desc wpr_buf; | ||
1180 | bool buf_loaded; | 1201 | bool buf_loaded; |
1181 | 1202 | ||
1182 | struct pmu_sha1_gid gid_info; | 1203 | struct pmu_sha1_gid gid_info; |
@@ -1294,4 +1315,6 @@ int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); | |||
1294 | void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable); | 1315 | void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable); |
1295 | int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, | 1316 | int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, |
1296 | u32 *var, u32 val); | 1317 | u32 *var, u32 val); |
1318 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | ||
1319 | void *param, u32 handle, u32 status); | ||
1297 | #endif /*__PMU_GK20A_H__*/ | 1320 | #endif /*__PMU_GK20A_H__*/ |