7 files changed, 18 insertions, 229 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index a257d709..65bf2976 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -36,7 +36,6 @@
 #include "dbg_gpu_gk20a.h"
 #include "regops_gk20a.h"
 
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 24cfc6ec..859a7b6a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -36,6 +36,7 @@
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/therm.h>
 
 #include <trace/events/gk20a.h>
 
@@ -323,7 +324,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
-        err = gk20a_init_therm_support(g);
+        err = nvgpu_init_therm_support(g);
         if (err) {
                 nvgpu_err(g, "failed to init gk20a therm");
                 goto done;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 204fd371..5bb91f62 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter;
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
 #include "pmu_gk20a.h"
-#include "therm_gk20a.h"
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
@@ -161,6 +160,18 @@ struct nvgpu_gpfifo_userdata {
 #define NVGPU_FB_MMU_FAULT_BUF_DISABLED                 0U
 #define NVGPU_FB_MMU_FAULT_BUF_ENABLED                  1U
 
+/* Parameters for init_elcg_mode/init_blcg_mode */
+enum {
+        ELCG_RUN,       /* clk always run, i.e. disable elcg */
+        ELCG_STOP,      /* clk is stopped */
+        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
+};
+
+enum {
+        BLCG_RUN,       /* clk always run, i.e. disable blcg */
+        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
+};
+
 struct gpu_ops {
         struct {
                 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -425,7 +436,6 @@ struct gpu_ops {
                                         struct nvgpu_mem *mem, u64 gpu_va);
                 void (*set_preemption_buffer_va)(struct gk20a *g,
                                         struct nvgpu_mem *mem, u64 gpu_va);
-                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 void (*load_tpc_mask)(struct gk20a *g);
                 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*trigger_suspend)(struct gk20a *g);
@@ -979,6 +989,8 @@ struct gpu_ops {
         } pramin;
         struct {
                 int (*init_therm_setup_hw)(struct gk20a *g);
+                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
+                void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 int (*elcg_init_idle_filters)(struct gk20a *g);
 #ifdef CONFIG_DEBUG_FS
                 void (*therm_debugfs_init)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5539b801..bb54e00e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -61,7 +61,6 @@
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
 
 #define BLK_SIZE (256)
@@ -4116,72 +4115,6 @@ int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                 gr_gk20a_add_zbc(g, gr, zbc_val));
 }
 
-void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
-{
-        u32 gate_ctrl;
-
-        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
-                return;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
-
-        switch (mode) {
-        case BLCG_RUN:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_blk_clk_m(),
-                                therm_gate_ctrl_blk_clk_run_f());
-                break;
-        case BLCG_AUTO:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_blk_clk_m(),
-                                therm_gate_ctrl_blk_clk_auto_f());
-                break;
-        default:
-                nvgpu_err(g,
-                        "invalid blcg mode %d", mode);
-                return;
-        }
-
-        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
-}
-
-void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
-{
-        u32 gate_ctrl;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
-
-        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
-                return;
-
-        switch (mode) {
-        case ELCG_RUN:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_run_f());
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_pwr_m(),
-                                /* set elpg to auto to meet hw expectation */
-                                therm_gate_ctrl_eng_pwr_auto_f());
-                break;
-        case ELCG_STOP:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_stop_f());
-                break;
-        case ELCG_AUTO:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_auto_f());
-                break;
-        default:
-                nvgpu_err(g,
-                        "invalid elcg mode %d", mode);
-        }
-
-        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
-}
-
 void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
 {
         u32 engine_idx;
@@ -4196,10 +4129,10 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
                 /* gr_engine supports both BLCG and ELCG */
                 if ((cgmode == BLCG_MODE) &&
                         (engine_info->engine_enum == ENGINE_GR_GK20A)) {
-                                gr_gk20a_init_blcg_mode(g, mode_config, active_engine_id);
+                                g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id);
                                 break;
                 } else if (cgmode == ELCG_MODE)
-                        g->ops.gr.init_elcg_mode(g, mode_config,
+                        g->ops.therm.init_elcg_mode(g, mode_config,
                                                 active_engine_id);
                 else
                         nvgpu_err(g, "invalid cg mode %d, config %d for "
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 2b31b6b6..9c9a3caa 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -126,17 +126,6 @@ enum {
 };
 
 enum {
-        ELCG_RUN,       /* clk always run, i.e. disable elcg */
-        ELCG_STOP,      /* clk is stopped */
-        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
-};
-
-enum {
-        BLCG_RUN,       /* clk always run, i.e. disable blcg */
-        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
-};
-
-enum {
         NVGPU_EVENT_ID_BPT_INT = 0,
         NVGPU_EVENT_ID_BPT_PAUSE,
         NVGPU_EVENT_ID_BLOCKING_SYNC,
@@ -609,9 +598,6 @@ int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g,
                 struct nvgpu_mem *inst_block);
 int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va);
 
-void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
-void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
-
 void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
 
 /* sm */
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
deleted file mode 100644
index b4a81aed..00000000
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * GK20A Therm
- *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-#include <nvgpu/utils.h>
-
-#include "gk20a.h"
-
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
-
-static int gk20a_init_therm_reset_enable_hw(struct gk20a *g)
-{
-        return 0;
-}
-
-static int gk20a_init_therm_setup_sw(struct gk20a *g)
-{
-        return 0;
-}
-
-int gk20a_init_therm_support(struct gk20a *g)
-{
-        u32 err;
-
-        nvgpu_log_fn(g, " ");
-
-        err = gk20a_init_therm_reset_enable_hw(g);
-        if (err)
-                return err;
-
-        err = gk20a_init_therm_setup_sw(g);
-        if (err)
-                return err;
-
-        if (g->ops.therm.init_therm_setup_hw)
-                err = g->ops.therm.init_therm_setup_hw(g);
-        if (err)
-                return err;
-
-#ifdef CONFIG_DEBUG_FS
-        if (g->ops.therm.therm_debugfs_init)
-            g->ops.therm.therm_debugfs_init(g);
-#endif
-
-        return err;
-}
-
-int gk20a_elcg_init_idle_filters(struct gk20a *g)
-{
-        u32 gate_ctrl, idle_filter;
-        u32 engine_id;
-        u32 active_engine_id = 0;
-        struct fifo_gk20a *f = &g->fifo;
-
-        nvgpu_log_fn(g, " ");
-
-        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
-                active_engine_id = f->active_engines_list[engine_id];
-                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
-
-                if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                        gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_delay_after_m(),
-                                therm_gate_ctrl_eng_delay_after_f(4));
-                }
-
-                /* 2 * (1 << 9) = 1024 clks */
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_exp_m(),
-                        therm_gate_ctrl_eng_idle_filt_exp_f(9));
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_mant_m(),
-                        therm_gate_ctrl_eng_idle_filt_mant_f(2));
-                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
-        }
-
-        /* default fecs_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
-        idle_filter &= ~therm_fecs_idle_filter_value_m();
-        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
-        /* default hubmmu_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
-        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
-        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h b/drivers/gpu/nvgpu/gk20a/therm_gk20a.h
deleted file mode 100644
index 303c28f4..00000000
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef THERM_GK20A_H
-#define THERM_GK20A_H
-
-struct gpu_ops;
-struct gk20a;
-
-int gk20a_elcg_init_idle_filters(struct gk20a *g);
-
-int gk20a_init_therm_support(struct gk20a *g);
-#endif /* THERM_GK20A_H */