diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 23 |
4 files changed, 0 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 53ed606d..43a6df0e 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -3467,18 +3467,6 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3467 | (struct nvgpu_alloc_obj_ctx_args *)buf); | 3467 | (struct nvgpu_alloc_obj_ctx_args *)buf); |
3468 | gk20a_idle(dev); | 3468 | gk20a_idle(dev); |
3469 | break; | 3469 | break; |
3470 | case NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX: | ||
3471 | err = gk20a_busy(dev); | ||
3472 | if (err) { | ||
3473 | dev_err(dev, | ||
3474 | "%s: failed to host gk20a for ioctl cmd: 0x%x", | ||
3475 | __func__, cmd); | ||
3476 | break; | ||
3477 | } | ||
3478 | err = ch->g->ops.gr.free_obj_ctx(ch, | ||
3479 | (struct nvgpu_free_obj_ctx_args *)buf); | ||
3480 | gk20a_idle(dev); | ||
3481 | break; | ||
3482 | case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: | 3470 | case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: |
3483 | { | 3471 | { |
3484 | struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = | 3472 | struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index f17128f0..832e03e9 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -155,7 +155,6 @@ struct channel_gk20a { | |||
155 | u64 userd_iova; | 155 | u64 userd_iova; |
156 | u64 userd_gpu_va; | 156 | u64 userd_gpu_va; |
157 | 157 | ||
158 | s32 num_objects; | ||
159 | u32 obj_class; /* we support only one obj per channel */ | 158 | u32 obj_class; /* we support only one obj per channel */ |
160 | 159 | ||
161 | struct priv_cmd_queue priv_cmd_q; | 160 | struct priv_cmd_queue priv_cmd_q; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 7699cd53..07752d66 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -196,8 +196,6 @@ struct gpu_ops { | |||
196 | void (*free_channel_ctx)(struct channel_gk20a *c); | 196 | void (*free_channel_ctx)(struct channel_gk20a *c); |
197 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 197 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
198 | struct nvgpu_alloc_obj_ctx_args *args); | 198 | struct nvgpu_alloc_obj_ctx_args *args); |
199 | int (*free_obj_ctx)(struct channel_gk20a *c, | ||
200 | struct nvgpu_free_obj_ctx_args *args); | ||
201 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, | 199 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, |
202 | struct channel_gk20a *c, u64 zcull_va, | 200 | struct channel_gk20a *c, u64 zcull_va, |
203 | u32 mode); | 201 | u32 mode); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0e8c1884..e6103479 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2957,7 +2957,6 @@ void gk20a_free_channel_ctx(struct channel_gk20a *c) | |||
2957 | 2957 | ||
2958 | memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a)); | 2958 | memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a)); |
2959 | 2959 | ||
2960 | c->num_objects = 0; | ||
2961 | c->first_init = false; | 2960 | c->first_init = false; |
2962 | } | 2961 | } |
2963 | 2962 | ||
@@ -3169,8 +3168,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3169 | c->first_init = true; | 3168 | c->first_init = true; |
3170 | } | 3169 | } |
3171 | 3170 | ||
3172 | c->num_objects++; | ||
3173 | |||
3174 | gk20a_dbg_fn("done"); | 3171 | gk20a_dbg_fn("done"); |
3175 | return 0; | 3172 | return 0; |
3176 | out: | 3173 | out: |
@@ -3182,25 +3179,6 @@ out: | |||
3182 | return err; | 3179 | return err; |
3183 | } | 3180 | } |
3184 | 3181 | ||
3185 | int gk20a_free_obj_ctx(struct channel_gk20a *c, | ||
3186 | struct nvgpu_free_obj_ctx_args *args) | ||
3187 | { | ||
3188 | gk20a_dbg_fn(""); | ||
3189 | |||
3190 | if (c->num_objects == 0) | ||
3191 | return 0; | ||
3192 | |||
3193 | c->num_objects--; | ||
3194 | |||
3195 | if (c->num_objects == 0) { | ||
3196 | c->first_init = false; | ||
3197 | gk20a_disable_channel(c); | ||
3198 | gr_gk20a_free_channel_patch_ctx(c); | ||
3199 | } | ||
3200 | |||
3201 | return 0; | ||
3202 | } | ||
3203 | |||
3204 | int gk20a_comptag_allocator_init(struct gk20a_comptag_allocator *allocator, | 3182 | int gk20a_comptag_allocator_init(struct gk20a_comptag_allocator *allocator, |
3205 | unsigned long size) | 3183 | unsigned long size) |
3206 | { | 3184 | { |
@@ -9082,7 +9060,6 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
9082 | gops->gr.get_gpc_tpc_mask = gr_gk20a_get_gpc_tpc_mask; | 9060 | gops->gr.get_gpc_tpc_mask = gr_gk20a_get_gpc_tpc_mask; |
9083 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; | 9061 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; |
9084 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; | 9062 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; |
9085 | gops->gr.free_obj_ctx = gk20a_free_obj_ctx; | ||
9086 | gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; | 9063 | gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; |
9087 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; | 9064 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; |
9088 | gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr; | 9065 | gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr; |