diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 10 |
2 files changed, 0 insertions, 98 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index 4d249524..ad8a6903 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h | |||
@@ -17,94 +17,6 @@ | |||
17 | #include <nvgpu/flcnif_cmn.h> | 17 | #include <nvgpu/flcnif_cmn.h> |
18 | #include "pmuif/gpmuif_pg_rppg.h" | 18 | #include "pmuif/gpmuif_pg_rppg.h" |
19 | 19 | ||
20 | /* ACR Commands/Message structures */ | ||
21 | |||
22 | enum { | ||
23 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0, | ||
24 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, | ||
25 | PMU_ACR_CMD_ID_RESERVED, | ||
26 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, | ||
27 | }; | ||
28 | |||
29 | /* | ||
30 | * Initializes the WPR region details | ||
31 | */ | ||
32 | struct pmu_acr_cmd_init_wpr_details { | ||
33 | u8 cmd_type; | ||
34 | u32 regionid; | ||
35 | u32 wproffset; | ||
36 | |||
37 | }; | ||
38 | |||
39 | /* | ||
40 | * falcon ID to bootstrap | ||
41 | */ | ||
42 | struct pmu_acr_cmd_bootstrap_falcon { | ||
43 | u8 cmd_type; | ||
44 | u32 flags; | ||
45 | u32 falconid; | ||
46 | }; | ||
47 | |||
48 | /* | ||
49 | * falcon ID to bootstrap | ||
50 | */ | ||
51 | struct pmu_acr_cmd_bootstrap_multiple_falcons { | ||
52 | u8 cmd_type; | ||
53 | u32 flags; | ||
54 | u32 falconidmask; | ||
55 | u32 usevamask; | ||
56 | struct falc_u64 wprvirtualbase; | ||
57 | }; | ||
58 | |||
59 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 | ||
60 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 | ||
61 | |||
62 | |||
63 | struct pmu_acr_cmd { | ||
64 | union { | ||
65 | u8 cmd_type; | ||
66 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; | ||
67 | struct pmu_acr_cmd_init_wpr_details init_wpr; | ||
68 | struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; | ||
69 | }; | ||
70 | }; | ||
71 | |||
72 | /* acr messages */ | ||
73 | |||
74 | /* | ||
75 | * returns the WPR region init information | ||
76 | */ | ||
77 | #define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 | ||
78 | |||
79 | /* | ||
80 | * Returns the Bootstrapped falcon ID to RM | ||
81 | */ | ||
82 | #define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 | ||
83 | |||
84 | /* | ||
85 | * Returns the WPR init status | ||
86 | */ | ||
87 | #define PMU_ACR_SUCCESS 0 | ||
88 | #define PMU_ACR_ERROR 1 | ||
89 | |||
90 | /* | ||
91 | * PMU notifies about bootstrap status of falcon | ||
92 | */ | ||
93 | struct pmu_acr_msg_bootstrap_falcon { | ||
94 | u8 msg_type; | ||
95 | union { | ||
96 | u32 errorcode; | ||
97 | u32 falconid; | ||
98 | }; | ||
99 | }; | ||
100 | |||
101 | struct pmu_acr_msg { | ||
102 | union { | ||
103 | u8 msg_type; | ||
104 | struct pmu_acr_msg_bootstrap_falcon acrmsg; | ||
105 | }; | ||
106 | }; | ||
107 | /*---------------------------------------------------------*/ | ||
108 | /* FECS mem override command*/ | 20 | /* FECS mem override command*/ |
109 | 21 | ||
110 | #define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 | 22 | #define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 87246f42..2f679970 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -124,16 +124,6 @@ struct pmu_ucode_desc_v1 { | |||
124 | u32 compressed; | 124 | u32 compressed; |
125 | }; | 125 | }; |
126 | 126 | ||
127 | /***************************** ACR ERROR CODES ******************************/ | ||
128 | /*! | ||
129 | * Error codes used in PMU-ACR Task | ||
130 | * | ||
131 | * LSF_ACR_INVALID_TRANSCFG_SETUP : Indicates that TRANSCFG Setup is not valid | ||
132 | * MAILBOX1 returns the CTXDMA ID of invalid setup | ||
133 | * | ||
134 | */ | ||
135 | #define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001) | ||
136 | |||
137 | #define PMU_PGENG_GR_BUFFER_IDX_INIT (0) | 127 | #define PMU_PGENG_GR_BUFFER_IDX_INIT (0) |
138 | #define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) | 128 | #define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) |
139 | #define PMU_PGENG_GR_BUFFER_IDX_FECS (2) | 129 | #define PMU_PGENG_GR_BUFFER_IDX_FECS (2) |