3 files changed, 3 insertions, 153 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
index def7bbea..d4af6bdb 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_api.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,7 +14,7 @@
 #ifndef __PMU_API_H__
 #define __PMU_API_H__
 
-#include "pmu_common.h"
+#include <nvgpu/flcnif_cmn.h>
 #include "pmuif/gpmuif_pg_rppg.h"
 
 /* PMU Command/Message Interfaces for Adaptive Power */
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h
deleted file mode 100644
index 3b3362c1..00000000
--- a/drivers/gpu/nvgpu/gk20a/pmu_common.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef __PMU_COMMON_H__
-#define __PMU_COMMON_H__
-
-#define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0
-
-struct falc_u64 {
-        u32 lo;
-        u32 hi;
-};
-
-struct falc_dma_addr {
-        u32 dma_base;
-        /*
-         * dma_base1 is 9-bit MSB for FB Base
-         * address for the transfer in FB after
-         * address using 49b FB address
-         */
-        u16 dma_base1;
-        u8 dma_offset;
-};
-
-struct pmu_mem_v0 {
-        u32 dma_base;
-        u8  dma_offset;
-        u8  dma_idx;
-};
-
-struct pmu_mem_v1 {
-        u32 dma_base;
-        u8  dma_offset;
-        u8  dma_idx;
-        u16 fb_size;
-};
-
-struct pmu_mem_v2 {
-        struct falc_dma_addr dma_addr;
-        u8  dma_idx;
-        u16 fb_size;
-};
-
-struct pmu_mem_desc_v0 {
-    /*!
-     * Start address of memory surface that is being communicated to the falcon.
-     */
-        struct falc_u64 dma_addr;
-    /*!
-     * Max allowed DMA transfer size (size of the memory surface). Accesses past
-     * this point may result in page faults and/or memory corruptions.
-     */
-        u16       dma_sizemax;
-    /*!
-     * DMA channel index to be used when accessing this surface.
-     */
-        u8        dma_idx;
-};
-
-struct pmu_dmem {
-        u16 size;
-        u32 offset;
-};
-
-struct flcn_u64 {
-        u32 lo;
-        u32 hi;
-};
-
-#define nv_flcn_u64 flcn_u64
-
-struct flcn_mem_desc_v0 {
-        struct flcn_u64 address;
-        u32 params;
-};
-
-#define nv_flcn_mem_desc flcn_mem_desc_v0
-
-struct pmu_allocation_v0 {
-        u8 pad[3];
-        u8 fb_mem_use;
-        struct {
-                struct pmu_dmem dmem;
-                struct pmu_mem_v0 fb;
-        } alloc;
-};
-
-struct pmu_allocation_v1 {
-        struct {
-                struct pmu_dmem dmem;
-                struct pmu_mem_v1 fb;
-        } alloc;
-};
-
-struct pmu_allocation_v2 {
-        struct {
-                struct pmu_dmem dmem;
-                struct pmu_mem_desc_v0 fb;
-        } alloc;
-};
-
-struct pmu_allocation_v3 {
-        struct {
-                struct pmu_dmem dmem;
-                struct flcn_mem_desc_v0 fb;
-        } alloc;
-};
-
-#define nv_pmu_allocation pmu_allocation_v3
-
-struct pmu_hdr {
-        u8 unit_id;
-        u8 size;
-        u8 ctrl_flags;
-        u8 seq_id;
-};
-
-#define nv_pmu_hdr pmu_hdr
-typedef u8 flcn_status;
-
-#define ALIGN_UP(v, gran)       (((v) + ((gran) - 1)) & ~((gran)-1))
-
-#define NV_UNSIGNED_ROUNDED_DIV(a, b)    (((a) + ((b) / 2)) / (b))
-
-#endif
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 84377d0b..dc23005e 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -23,7 +23,7 @@
 
 #include <linux/version.h>
 #include "pmu_api.h"
-#include "pmu_common.h"
+#include <nvgpu/flcnif_cmn.h>
 #include "pmuif/nvgpu_gpmu_cmdif.h"
 
 /* defined by pmu hw spec */
@@ -124,21 +124,6 @@ struct pmu_ucode_desc_v1 {
         u32 compressed;
 };
 
-#define PMU_DMEM_ALLOC_ALIGNMENT        (4)
-#define PMU_DMEM_ALIGNMENT              (4)
-
-#define PMU_CMD_FLAGS_PMU_MASK          (0xF0)
-
-#define PMU_CMD_FLAGS_STATUS            BIT(0)
-#define PMU_CMD_FLAGS_INTR              BIT(1)
-#define PMU_CMD_FLAGS_EVENT             BIT(2)
-#define PMU_CMD_FLAGS_WATERMARK         BIT(3)
-
-#define PMU_MSG_HDR_SIZE        sizeof(struct pmu_hdr)
-#define PMU_CMD_HDR_SIZE        sizeof(struct pmu_hdr)
-
-
-
 /***************************** ACR ERROR CODES  ******************************/
 /*!
  * Error codes used in PMU-ACR Task