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-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 5bd43510..27d27007 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * GK20A PMU (aka. gPMU outside gk20a context) 4 * GK20A PMU (aka. gPMU outside gk20a context)
5 * 5 *
6 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. 6 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
7 * 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a 8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"), 9 * copy of this software and associated documentation files (the "Software"),
@@ -69,7 +69,7 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
69 69
70void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); 70void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
71int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, 71int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
72 u32 *var, u32 val); 72 void *var, u8 val);
73void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, 73void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
74 void *param, u32 handle, u32 status); 74 void *param, u32 handle, u32 status);
75void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, 75void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,