5 files changed, 14 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 192f4c3e..5a888303 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -68,7 +68,6 @@ struct nvgpu_ctxsw_trace_filter;
 #include "ce2_gk20a.h"
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
-#include "pmu_gk20a.h"
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
@@ -1025,6 +1024,15 @@ struct gpu_ops {
                         u32 id, u32 *token);
                 int (*pmu_mutex_release)(struct nvgpu_pmu *pmu,
                         u32 id, u32 *token);
+                bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu);
+                void (*pmu_isr)(struct gk20a *g);
+                void (*pmu_init_perfmon_counter)(struct gk20a *g);
+                void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id);
+                u32  (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id);
+                void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id);
+                void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu);
+                void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu);
+                void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable);
                 int (*init_wpr_region)(struct gk20a *g);
                 int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
                 void (*write_dmatrfbase)(struct gk20a *g, u32 addr);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index cdc00bbd..d4c461af 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3763,7 +3763,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
         }
 
         /* update zbc */
-        gk20a_pmu_save_zbc(g, entries);
+        g->ops.gr.pmu_save_zbc(g, entries);
 
 clean_up:
         ret = gk20a_fifo_enable_engine_activity(g, gr_info);
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index a0eae127..f7631a9c 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -67,7 +67,7 @@ void mc_gk20a_isr_stall(struct gk20a *g)
                 gk20a_fifo_isr(g);
         }
         if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) {
-                gk20a_pmu_isr(g);
+                g->ops.pmu.pmu_isr(g);
         }
         if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) {
                 g->ops.priv_ring.isr(g);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 9ec4c867..64e4a567 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -37,6 +37,7 @@
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
+#include "pmu_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
@@ -137,7 +138,7 @@ u32 gk20a_pmu_get_irqdest(struct gk20a *g)
         return intr_dest;
 }
 
-void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
+void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
         u32 intr_mask;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index d9c53c28..ee7ee8c7 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -67,9 +67,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu);
 void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
 void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
 
-void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
-int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
-                                 void *var, u8 val);
+void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
 void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
                                 void *param, u32 handle, u32 status);
 void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,