diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 4 |
5 files changed, 14 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 192f4c3e..5a888303 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -68,7 +68,6 @@ struct nvgpu_ctxsw_trace_filter; | |||
68 | #include "ce2_gk20a.h" | 68 | #include "ce2_gk20a.h" |
69 | #include "fifo_gk20a.h" | 69 | #include "fifo_gk20a.h" |
70 | #include "tsg_gk20a.h" | 70 | #include "tsg_gk20a.h" |
71 | #include "pmu_gk20a.h" | ||
72 | #include "clk/clk.h" | 71 | #include "clk/clk.h" |
73 | #include "perf/perf.h" | 72 | #include "perf/perf.h" |
74 | #include "pmgr/pmgr.h" | 73 | #include "pmgr/pmgr.h" |
@@ -1025,6 +1024,15 @@ struct gpu_ops { | |||
1025 | u32 id, u32 *token); | 1024 | u32 id, u32 *token); |
1026 | int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, | 1025 | int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, |
1027 | u32 id, u32 *token); | 1026 | u32 id, u32 *token); |
1027 | bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu); | ||
1028 | void (*pmu_isr)(struct gk20a *g); | ||
1029 | void (*pmu_init_perfmon_counter)(struct gk20a *g); | ||
1030 | void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id); | ||
1031 | u32 (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id); | ||
1032 | void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id); | ||
1033 | void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu); | ||
1034 | void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu); | ||
1035 | void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable); | ||
1028 | int (*init_wpr_region)(struct gk20a *g); | 1036 | int (*init_wpr_region)(struct gk20a *g); |
1029 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); | 1037 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); |
1030 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); | 1038 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index cdc00bbd..d4c461af 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3763,7 +3763,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | |||
3763 | } | 3763 | } |
3764 | 3764 | ||
3765 | /* update zbc */ | 3765 | /* update zbc */ |
3766 | gk20a_pmu_save_zbc(g, entries); | 3766 | g->ops.gr.pmu_save_zbc(g, entries); |
3767 | 3767 | ||
3768 | clean_up: | 3768 | clean_up: |
3769 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | 3769 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index a0eae127..f7631a9c 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -67,7 +67,7 @@ void mc_gk20a_isr_stall(struct gk20a *g) | |||
67 | gk20a_fifo_isr(g); | 67 | gk20a_fifo_isr(g); |
68 | } | 68 | } |
69 | if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { | 69 | if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { |
70 | gk20a_pmu_isr(g); | 70 | g->ops.pmu.pmu_isr(g); |
71 | } | 71 | } |
72 | if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { | 72 | if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { |
73 | g->ops.priv_ring.isr(g); | 73 | g->ops.priv_ring.isr(g); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 9ec4c867..64e4a567 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #include "gk20a.h" | 38 | #include "gk20a.h" |
39 | #include "gr_gk20a.h" | 39 | #include "gr_gk20a.h" |
40 | #include "pmu_gk20a.h" | ||
40 | 41 | ||
41 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> | 43 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> |
@@ -137,7 +138,7 @@ u32 gk20a_pmu_get_irqdest(struct gk20a *g) | |||
137 | return intr_dest; | 138 | return intr_dest; |
138 | } | 139 | } |
139 | 140 | ||
140 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) | 141 | void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) |
141 | { | 142 | { |
142 | struct gk20a *g = gk20a_from_pmu(pmu); | 143 | struct gk20a *g = gk20a_from_pmu(pmu); |
143 | u32 intr_mask; | 144 | u32 intr_mask; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index d9c53c28..ee7ee8c7 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -67,9 +67,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu); | |||
67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); | 67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); |
68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); | 68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); |
69 | 69 | ||
70 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); | 70 | void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); |
71 | int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | ||
72 | void *var, u8 val); | ||
73 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | 71 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, |
74 | void *param, u32 handle, u32 status); | 72 | void *param, u32 handle, u32 status); |
75 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 73 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |