diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/cde_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/debug_gk20a.c | 103 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/debug_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 177 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_allocator.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_allocator.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_scale.c | 3 |
9 files changed, 117 insertions, 185 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c index 6f8c160c..844718a7 100644 --- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c | |||
@@ -1653,6 +1653,9 @@ void gk20a_cde_debugfs_init(struct device *dev) | |||
1653 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 1653 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
1654 | struct gk20a *g = get_gk20a(dev); | 1654 | struct gk20a *g = get_gk20a(dev); |
1655 | 1655 | ||
1656 | if (!platform->has_cde) | ||
1657 | return; | ||
1658 | |||
1656 | debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO, | 1659 | debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO, |
1657 | platform->debugfs, &g->cde_app.shader_parameter); | 1660 | platform->debugfs, &g->cde_app.shader_parameter); |
1658 | debugfs_create_u32("cde_ctx_count", S_IWUSR | S_IRUGO, | 1661 | debugfs_create_u32("cde_ctx_count", S_IWUSR | S_IRUGO, |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 8548ae84..109ec240 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -710,6 +710,9 @@ void gk20a_ce_debugfs_init(struct device *dev) | |||
710 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 710 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
711 | struct gk20a *g = get_gk20a(dev); | 711 | struct gk20a *g = get_gk20a(dev); |
712 | 712 | ||
713 | if (!platform->has_ce) | ||
714 | return; | ||
715 | |||
713 | debugfs_create_u32("ce_app_ctx_count", S_IWUSR | S_IRUGO, | 716 | debugfs_create_u32("ce_app_ctx_count", S_IWUSR | S_IRUGO, |
714 | platform->debugfs, &g->ce_app.ctx_count); | 717 | platform->debugfs, &g->ce_app.ctx_count); |
715 | debugfs_create_u32("ce_app_state", S_IWUSR | S_IRUGO, | 718 | debugfs_create_u32("ce_app_state", S_IWUSR | S_IRUGO, |
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c index 93580a7f..9a84e2e3 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c | |||
@@ -386,30 +386,101 @@ void gk20a_init_debug_ops(struct gpu_ops *gops) | |||
386 | gops->debug.show_dump = gk20a_debug_show_dump; | 386 | gops->debug.show_dump = gk20a_debug_show_dump; |
387 | } | 387 | } |
388 | 388 | ||
389 | void gk20a_debug_init(struct device *dev) | 389 | void gk20a_debug_init(struct device *dev, const char *debugfs_symlink) |
390 | { | 390 | { |
391 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 391 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
392 | #ifdef CONFIG_DEBUG_FS | ||
393 | struct gk20a *g = platform->g; | ||
394 | #endif | ||
392 | 395 | ||
393 | platform->debugfs = debugfs_create_dir(dev_name(dev), NULL); | 396 | platform->debugfs = debugfs_create_dir(dev_name(dev), NULL); |
394 | if (platform->debugfs) { | 397 | if (!platform->debugfs) |
398 | return; | ||
399 | |||
400 | if (debugfs_symlink) | ||
395 | platform->debugfs_alias = | 401 | platform->debugfs_alias = |
396 | debugfs_create_symlink("gpu.0", NULL, dev_name(dev)); | 402 | debugfs_create_symlink(debugfs_symlink, |
403 | NULL, dev_name(dev)); | ||
397 | 404 | ||
398 | debugfs_create_file("status", S_IRUGO, platform->debugfs, | 405 | debugfs_create_file("status", S_IRUGO, platform->debugfs, |
399 | dev, &gk20a_debug_fops); | 406 | dev, &gk20a_debug_fops); |
400 | debugfs_create_file("gr_status", S_IRUGO, platform->debugfs, | 407 | debugfs_create_file("gr_status", S_IRUGO, platform->debugfs, |
401 | dev, &gk20a_gr_debug_fops); | 408 | dev, &gk20a_gr_debug_fops); |
402 | debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, | 409 | debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, |
403 | platform->debugfs, &gk20a_debug_trace_cmdbuf); | 410 | platform->debugfs, &gk20a_debug_trace_cmdbuf); |
404 | 411 | ||
405 | debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR, | 412 | debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR, |
406 | platform->debugfs, &platform->ch_wdt_timeout_ms); | 413 | platform->debugfs, &platform->ch_wdt_timeout_ms); |
407 | 414 | ||
408 | #if defined(GK20A_DEBUG) | 415 | #if defined(GK20A_DEBUG) |
409 | debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR, | 416 | debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR, |
410 | platform->debugfs, &gk20a_dbg_mask); | 417 | platform->debugfs, &gk20a_dbg_mask); |
411 | debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR, | 418 | debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR, |
412 | platform->debugfs, &gk20a_dbg_ftrace); | 419 | platform->debugfs, &gk20a_dbg_ftrace); |
413 | #endif | 420 | #endif |
414 | } | 421 | |
422 | #ifdef CONFIG_DEBUG_FS | ||
423 | spin_lock_init(&g->debugfs_lock); | ||
424 | |||
425 | g->mm.ltc_enabled = true; | ||
426 | g->mm.ltc_enabled_debug = true; | ||
427 | |||
428 | g->debugfs_ltc_enabled = | ||
429 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, | ||
430 | platform->debugfs, | ||
431 | &g->mm.ltc_enabled_debug); | ||
432 | |||
433 | g->debugfs_gr_idle_timeout_default = | ||
434 | debugfs_create_u32("gr_idle_timeout_default_us", | ||
435 | S_IRUGO|S_IWUSR, platform->debugfs, | ||
436 | &g->gr_idle_timeout_default); | ||
437 | g->debugfs_timeouts_enabled = | ||
438 | debugfs_create_bool("timeouts_enabled", | ||
439 | S_IRUGO|S_IWUSR, | ||
440 | platform->debugfs, | ||
441 | &g->timeouts_enabled); | ||
442 | |||
443 | g->debugfs_bypass_smmu = | ||
444 | debugfs_create_bool("bypass_smmu", | ||
445 | S_IRUGO|S_IWUSR, | ||
446 | platform->debugfs, | ||
447 | &g->mm.bypass_smmu); | ||
448 | g->debugfs_disable_bigpage = | ||
449 | debugfs_create_bool("disable_bigpage", | ||
450 | S_IRUGO|S_IWUSR, | ||
451 | platform->debugfs, | ||
452 | &g->mm.disable_bigpage); | ||
453 | |||
454 | g->debugfs_timeslice_low_priority_us = | ||
455 | debugfs_create_u32("timeslice_low_priority_us", | ||
456 | S_IRUGO|S_IWUSR, | ||
457 | platform->debugfs, | ||
458 | &g->timeslice_low_priority_us); | ||
459 | g->debugfs_timeslice_medium_priority_us = | ||
460 | debugfs_create_u32("timeslice_medium_priority_us", | ||
461 | S_IRUGO|S_IWUSR, | ||
462 | platform->debugfs, | ||
463 | &g->timeslice_medium_priority_us); | ||
464 | g->debugfs_timeslice_high_priority_us = | ||
465 | debugfs_create_u32("timeslice_high_priority_us", | ||
466 | S_IRUGO|S_IWUSR, | ||
467 | platform->debugfs, | ||
468 | &g->timeslice_high_priority_us); | ||
469 | g->debugfs_runlist_interleave = | ||
470 | debugfs_create_bool("runlist_interleave", | ||
471 | S_IRUGO|S_IWUSR, | ||
472 | platform->debugfs, | ||
473 | &g->runlist_interleave); | ||
474 | |||
475 | gr_gk20a_debugfs_init(g); | ||
476 | gk20a_pmu_debugfs_init(g->dev); | ||
477 | gk20a_railgating_debugfs_init(g->dev); | ||
478 | gk20a_cde_debugfs_init(g->dev); | ||
479 | gk20a_ce_debugfs_init(g->dev); | ||
480 | gk20a_alloc_debugfs_init(g->dev); | ||
481 | gk20a_mm_debugfs_init(g->dev); | ||
482 | gk20a_fifo_debugfs_init(g->dev); | ||
483 | gk20a_sched_debugfs_init(g->dev); | ||
484 | #endif | ||
485 | |||
415 | } | 486 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h index e83076b8..ac8e3236 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h | |||
@@ -35,7 +35,7 @@ void gk20a_debug_output(struct gk20a_debug_output *o, | |||
35 | void gk20a_debug_dump(struct device *pdev); | 35 | void gk20a_debug_dump(struct device *pdev); |
36 | void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); | 36 | void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); |
37 | int gk20a_gr_debug_dump(struct device *pdev); | 37 | int gk20a_gr_debug_dump(struct device *pdev); |
38 | void gk20a_debug_init(struct device *dev); | 38 | void gk20a_debug_init(struct device *dev, const char *debugfs_symlink); |
39 | void gk20a_init_debug_ops(struct gpu_ops *gops); | 39 | void gk20a_init_debug_ops(struct gpu_ops *gops); |
40 | void gk20a_debug_dump_device(void *dev); | 40 | void gk20a_debug_dump_device(void *dev); |
41 | 41 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 1fe1d330..f6bb9445 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <linux/version.h> | 45 | #include <linux/version.h> |
46 | 46 | ||
47 | #include "gk20a.h" | 47 | #include "gk20a.h" |
48 | #include "nvgpu_common.h" | ||
48 | #include "debug_gk20a.h" | 49 | #include "debug_gk20a.h" |
49 | #include "ctrl_gk20a.h" | 50 | #include "ctrl_gk20a.h" |
50 | #include "hw_mc_gk20a.h" | 51 | #include "hw_mc_gk20a.h" |
@@ -83,8 +84,6 @@ | |||
83 | 84 | ||
84 | #define GK20A_NUM_CDEVS 7 | 85 | #define GK20A_NUM_CDEVS 7 |
85 | 86 | ||
86 | #define EMC3D_DEFAULT_RATIO 750 | ||
87 | |||
88 | #if defined(GK20A_DEBUG) | 87 | #if defined(GK20A_DEBUG) |
89 | u32 gk20a_dbg_mask = GK20A_DEFAULT_DBG_MASK; | 88 | u32 gk20a_dbg_mask = GK20A_DEFAULT_DBG_MASK; |
90 | u32 gk20a_dbg_ftrace; | 89 | u32 gk20a_dbg_ftrace; |
@@ -144,11 +143,14 @@ static const struct file_operations railgate_residency_fops = { | |||
144 | .release = single_release, | 143 | .release = single_release, |
145 | }; | 144 | }; |
146 | 145 | ||
147 | static int gk20a_railgating_debugfs_init(struct device *dev) | 146 | int gk20a_railgating_debugfs_init(struct device *dev) |
148 | { | 147 | { |
149 | struct dentry *d; | 148 | struct dentry *d; |
150 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 149 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
151 | 150 | ||
151 | if (!platform->can_railgate) | ||
152 | return 0; | ||
153 | |||
152 | d = debugfs_create_file( | 154 | d = debugfs_create_file( |
153 | "railgate_residency", S_IRUGO|S_IWUSR, platform->debugfs, dev, | 155 | "railgate_residency", S_IRUGO|S_IWUSR, platform->debugfs, dev, |
154 | &railgate_residency_fops); | 156 | &railgate_residency_fops); |
@@ -740,32 +742,15 @@ static int gk20a_init_support(struct platform_device *dev) | |||
740 | goto fail; | 742 | goto fail; |
741 | } | 743 | } |
742 | 744 | ||
743 | g->regs_saved = g->regs; | ||
744 | g->bar1_saved = g->bar1; | ||
745 | |||
746 | /* Get interrupt numbers */ | ||
747 | g->irq_nonstall = platform_get_irq(dev, 1); | ||
748 | if (g->irq_stall < 0 || g->irq_nonstall < 0) { | ||
749 | err = -ENXIO; | ||
750 | goto fail; | ||
751 | } | ||
752 | |||
753 | if (tegra_cpu_is_asim()) { | 745 | if (tegra_cpu_is_asim()) { |
754 | err = gk20a_init_sim_support(dev); | 746 | err = gk20a_init_sim_support(dev); |
755 | if (err) | 747 | if (err) |
756 | goto fail; | 748 | goto fail; |
757 | } | 749 | } |
758 | 750 | ||
759 | mutex_init(&g->dbg_sessions_lock); | ||
760 | mutex_init(&g->client_lock); | ||
761 | mutex_init(&g->ch_wdt_lock); | ||
762 | mutex_init(&g->poweroff_lock); | ||
763 | |||
764 | g->remove_support = gk20a_remove_support; | ||
765 | return 0; | 751 | return 0; |
766 | 752 | ||
767 | fail: | 753 | fail: |
768 | gk20a_remove_support(&dev->dev); | ||
769 | return err; | 754 | return err; |
770 | } | 755 | } |
771 | 756 | ||
@@ -1449,13 +1434,13 @@ int gk20a_pm_init(struct device *dev) | |||
1449 | return err; | 1434 | return err; |
1450 | } | 1435 | } |
1451 | 1436 | ||
1452 | static int gk20a_secure_page_alloc(struct platform_device *pdev) | 1437 | int gk20a_secure_page_alloc(struct device *dev) |
1453 | { | 1438 | { |
1454 | struct gk20a_platform *platform = platform_get_drvdata(pdev); | 1439 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
1455 | int err = 0; | 1440 | int err = 0; |
1456 | 1441 | ||
1457 | if (platform->secure_page_alloc) { | 1442 | if (platform->secure_page_alloc) { |
1458 | err = platform->secure_page_alloc(&pdev->dev); | 1443 | err = platform->secure_page_alloc(dev); |
1459 | if (!err) | 1444 | if (!err) |
1460 | platform->secure_alloc_ready = true; | 1445 | platform->secure_alloc_ready = true; |
1461 | } | 1446 | } |
@@ -1499,9 +1484,6 @@ static int gk20a_probe(struct platform_device *dev) | |||
1499 | return -ENOMEM; | 1484 | return -ENOMEM; |
1500 | } | 1485 | } |
1501 | 1486 | ||
1502 | init_waitqueue_head(&gk20a->sw_irq_stall_last_handled_wq); | ||
1503 | init_waitqueue_head(&gk20a->sw_irq_nonstall_last_handled_wq); | ||
1504 | |||
1505 | set_gk20a(dev, gk20a); | 1487 | set_gk20a(dev, gk20a); |
1506 | gk20a->dev = &dev->dev; | 1488 | gk20a->dev = &dev->dev; |
1507 | 1489 | ||
@@ -1509,6 +1491,7 @@ static int gk20a_probe(struct platform_device *dev) | |||
1509 | gk20a->irq_nonstall = platform_get_irq(dev, 1); | 1491 | gk20a->irq_nonstall = platform_get_irq(dev, 1); |
1510 | if (gk20a->irq_stall < 0 || gk20a->irq_nonstall < 0) | 1492 | if (gk20a->irq_stall < 0 || gk20a->irq_nonstall < 0) |
1511 | return -ENXIO; | 1493 | return -ENXIO; |
1494 | |||
1512 | err = devm_request_threaded_irq(&dev->dev, | 1495 | err = devm_request_threaded_irq(&dev->dev, |
1513 | gk20a->irq_stall, | 1496 | gk20a->irq_stall, |
1514 | gk20a_intr_isr_stall, | 1497 | gk20a_intr_isr_stall, |
@@ -1535,36 +1518,19 @@ static int gk20a_probe(struct platform_device *dev) | |||
1535 | if (gk20a->irq_stall != gk20a->irq_nonstall) | 1518 | if (gk20a->irq_stall != gk20a->irq_nonstall) |
1536 | disable_irq(gk20a->irq_nonstall); | 1519 | disable_irq(gk20a->irq_nonstall); |
1537 | 1520 | ||
1538 | err = gk20a_user_init(&dev->dev, INTERFACE_NAME, &nvgpu_class); | 1521 | err = gk20a_init_support(dev); |
1539 | if (err) | 1522 | if (err) |
1540 | return err; | 1523 | return err; |
1541 | 1524 | ||
1542 | gk20a_init_support(dev); | ||
1543 | |||
1544 | init_rwsem(&gk20a->busy_lock); | ||
1545 | mutex_init(&platform->railgate_lock); | ||
1546 | |||
1547 | spin_lock_init(&gk20a->mc_enable_lock); | ||
1548 | |||
1549 | #ifdef CONFIG_RESET_CONTROLLER | 1525 | #ifdef CONFIG_RESET_CONTROLLER |
1550 | platform->reset_control = devm_reset_control_get(&dev->dev, NULL); | 1526 | platform->reset_control = devm_reset_control_get(&dev->dev, NULL); |
1551 | if (IS_ERR(platform->reset_control)) | 1527 | if (IS_ERR(platform->reset_control)) |
1552 | platform->reset_control = NULL; | 1528 | platform->reset_control = NULL; |
1553 | #endif | 1529 | #endif |
1554 | 1530 | ||
1555 | gk20a_debug_init(&dev->dev); | 1531 | err = nvgpu_probe(gk20a, "gpu.0", INTERFACE_NAME, &nvgpu_class); |
1556 | |||
1557 | /* Initialize the platform interface. */ | ||
1558 | err = platform->probe(&dev->dev); | ||
1559 | if (err) { | ||
1560 | dev_err(&dev->dev, "platform probe failed"); | ||
1561 | return err; | ||
1562 | } | ||
1563 | |||
1564 | err = gk20a_secure_page_alloc(dev); | ||
1565 | if (err) | 1532 | if (err) |
1566 | dev_err(&dev->dev, | 1533 | return err; |
1567 | "failed to allocate secure buffer %d\n", err); | ||
1568 | 1534 | ||
1569 | err = gk20a_pm_init(&dev->dev); | 1535 | err = gk20a_pm_init(&dev->dev); |
1570 | if (err) { | 1536 | if (err) { |
@@ -1572,127 +1538,8 @@ static int gk20a_probe(struct platform_device *dev) | |||
1572 | return err; | 1538 | return err; |
1573 | } | 1539 | } |
1574 | 1540 | ||
1575 | gk20a->emc3d_ratio = EMC3D_DEFAULT_RATIO; | ||
1576 | |||
1577 | /* Initialise scaling */ | ||
1578 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | ||
1579 | gk20a_scale_init(&dev->dev); | ||
1580 | |||
1581 | /* Set DMA parameters to allow larger sgt lists */ | ||
1582 | dev->dev.dma_parms = &gk20a->dma_parms; | ||
1583 | dma_set_max_seg_size(&dev->dev, UINT_MAX); | ||
1584 | |||
1585 | gk20a->gr_idle_timeout_default = | ||
1586 | CONFIG_GK20A_DEFAULT_TIMEOUT; | ||
1587 | if (tegra_platform_is_silicon()) | ||
1588 | gk20a->timeouts_enabled = true; | ||
1589 | |||
1590 | gk20a->runlist_interleave = true; | ||
1591 | |||
1592 | gk20a->timeslice_low_priority_us = 1300; | ||
1593 | gk20a->timeslice_medium_priority_us = 2600; | ||
1594 | gk20a->timeslice_high_priority_us = 5200; | ||
1595 | |||
1596 | /* Set up initial power settings. For non-slicon platforms, disable * | ||
1597 | * power features and for silicon platforms, read from platform data */ | ||
1598 | gk20a->slcg_enabled = | ||
1599 | tegra_platform_is_silicon() ? platform->enable_slcg : false; | ||
1600 | gk20a->blcg_enabled = | ||
1601 | tegra_platform_is_silicon() ? platform->enable_blcg : false; | ||
1602 | gk20a->elcg_enabled = | ||
1603 | tegra_platform_is_silicon() ? platform->enable_elcg : false; | ||
1604 | gk20a->elpg_enabled = | ||
1605 | tegra_platform_is_silicon() ? platform->enable_elpg : false; | ||
1606 | gk20a->aelpg_enabled = | ||
1607 | tegra_platform_is_silicon() ? platform->enable_aelpg : false; | ||
1608 | |||
1609 | /* set default values to aelpg parameters */ | ||
1610 | gk20a->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; | ||
1611 | gk20a->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; | ||
1612 | gk20a->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; | ||
1613 | gk20a->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; | ||
1614 | gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; | ||
1615 | |||
1616 | if (platform->late_probe) { | ||
1617 | err = platform->late_probe(&dev->dev); | ||
1618 | if (err) { | ||
1619 | dev_err(&dev->dev, "late probe failed"); | ||
1620 | return err; | ||
1621 | } | ||
1622 | } | ||
1623 | |||
1624 | gk20a_create_sysfs(&dev->dev); | ||
1625 | |||
1626 | gk20a->mm.bypass_smmu = platform->bypass_smmu; | ||
1627 | gk20a->mm.disable_bigpage = platform->disable_bigpage; | ||
1628 | gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode(); | 1541 | gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode(); |
1629 | 1542 | ||
1630 | #ifdef CONFIG_DEBUG_FS | ||
1631 | spin_lock_init(&gk20a->debugfs_lock); | ||
1632 | gk20a->mm.ltc_enabled = true; | ||
1633 | gk20a->mm.ltc_enabled_debug = true; | ||
1634 | gk20a->debugfs_ltc_enabled = | ||
1635 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, | ||
1636 | platform->debugfs, | ||
1637 | &gk20a->mm.ltc_enabled_debug); | ||
1638 | gk20a->mm.ltc_enabled_debug = true; | ||
1639 | gk20a->debugfs_gr_idle_timeout_default = | ||
1640 | debugfs_create_u32("gr_idle_timeout_default_us", | ||
1641 | S_IRUGO|S_IWUSR, platform->debugfs, | ||
1642 | &gk20a->gr_idle_timeout_default); | ||
1643 | gk20a->debugfs_timeouts_enabled = | ||
1644 | debugfs_create_bool("timeouts_enabled", | ||
1645 | S_IRUGO|S_IWUSR, | ||
1646 | platform->debugfs, | ||
1647 | &gk20a->timeouts_enabled); | ||
1648 | gk20a->debugfs_bypass_smmu = | ||
1649 | debugfs_create_bool("bypass_smmu", | ||
1650 | S_IRUGO|S_IWUSR, | ||
1651 | platform->debugfs, | ||
1652 | &gk20a->mm.bypass_smmu); | ||
1653 | gk20a->debugfs_disable_bigpage = | ||
1654 | debugfs_create_bool("disable_bigpage", | ||
1655 | S_IRUGO|S_IWUSR, | ||
1656 | platform->debugfs, | ||
1657 | &gk20a->mm.disable_bigpage); | ||
1658 | |||
1659 | gk20a->debugfs_timeslice_low_priority_us = | ||
1660 | debugfs_create_u32("timeslice_low_priority_us", | ||
1661 | S_IRUGO|S_IWUSR, | ||
1662 | platform->debugfs, | ||
1663 | &gk20a->timeslice_low_priority_us); | ||
1664 | |||
1665 | gk20a->debugfs_timeslice_medium_priority_us = | ||
1666 | debugfs_create_u32("timeslice_medium_priority_us", | ||
1667 | S_IRUGO|S_IWUSR, | ||
1668 | platform->debugfs, | ||
1669 | &gk20a->timeslice_medium_priority_us); | ||
1670 | |||
1671 | gk20a->debugfs_timeslice_high_priority_us = | ||
1672 | debugfs_create_u32("timeslice_high_priority_us", | ||
1673 | S_IRUGO|S_IWUSR, | ||
1674 | platform->debugfs, | ||
1675 | &gk20a->timeslice_high_priority_us); | ||
1676 | |||
1677 | gk20a->debugfs_runlist_interleave = | ||
1678 | debugfs_create_bool("runlist_interleave", | ||
1679 | S_IRUGO|S_IWUSR, | ||
1680 | platform->debugfs, | ||
1681 | &gk20a->runlist_interleave); | ||
1682 | |||
1683 | gr_gk20a_debugfs_init(gk20a); | ||
1684 | gk20a_pmu_debugfs_init(&dev->dev); | ||
1685 | gk20a_railgating_debugfs_init(&dev->dev); | ||
1686 | gk20a_cde_debugfs_init(&dev->dev); | ||
1687 | gk20a_ce_debugfs_init(&dev->dev); | ||
1688 | gk20a_alloc_debugfs_init(dev); | ||
1689 | gk20a_mm_debugfs_init(&dev->dev); | ||
1690 | gk20a_fifo_debugfs_init(&dev->dev); | ||
1691 | gk20a_sched_debugfs_init(&dev->dev); | ||
1692 | #endif | ||
1693 | |||
1694 | gk20a_init_gr(gk20a); | ||
1695 | |||
1696 | return 0; | 1543 | return 0; |
1697 | } | 1544 | } |
1698 | 1545 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c255f8f8..669ef1b9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1205,4 +1205,9 @@ static inline void gk20a_channel_trace_sched_param( | |||
1205 | ch->ch_ctx.gr_ctx->compute_preempt_mode : 0)); | 1205 | ch->ch_ctx.gr_ctx->compute_preempt_mode : 0)); |
1206 | } | 1206 | } |
1207 | 1207 | ||
1208 | #ifdef CONFIG_DEBUG_FS | ||
1209 | int gk20a_railgating_debugfs_init(struct device *dev); | ||
1210 | #endif | ||
1211 | |||
1212 | int gk20a_secure_page_alloc(struct device *dev); | ||
1208 | #endif /* GK20A_H */ | 1213 | #endif /* GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c index d9e38200..3b20fa2e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c | |||
@@ -168,9 +168,9 @@ void gk20a_fini_alloc_debug(struct gk20a_allocator *a) | |||
168 | debugfs_remove(a->debugfs_entry); | 168 | debugfs_remove(a->debugfs_entry); |
169 | } | 169 | } |
170 | 170 | ||
171 | void gk20a_alloc_debugfs_init(struct platform_device *pdev) | 171 | void gk20a_alloc_debugfs_init(struct device *dev) |
172 | { | 172 | { |
173 | struct gk20a_platform *platform = platform_get_drvdata(pdev); | 173 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
174 | struct dentry *gpu_root = platform->debugfs; | 174 | struct dentry *gpu_root = platform->debugfs; |
175 | 175 | ||
176 | gk20a_alloc_debugfs_root = debugfs_create_dir("allocators", gpu_root); | 176 | gk20a_alloc_debugfs_root = debugfs_create_dir("allocators", gpu_root); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h index fbfda881..93865190 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h | |||
@@ -210,7 +210,7 @@ static inline void gk20a_alloc_disable_dbg(struct gk20a_allocator *a) | |||
210 | */ | 210 | */ |
211 | extern u32 gk20a_alloc_tracing_on; | 211 | extern u32 gk20a_alloc_tracing_on; |
212 | 212 | ||
213 | void gk20a_alloc_debugfs_init(struct platform_device *pdev); | 213 | void gk20a_alloc_debugfs_init(struct device *dev); |
214 | 214 | ||
215 | #define gk20a_alloc_trace_func() \ | 215 | #define gk20a_alloc_trace_func() \ |
216 | do { \ | 216 | do { \ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c index ec9ca5db..ac28d967 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c | |||
@@ -319,6 +319,9 @@ void gk20a_scale_init(struct device *dev) | |||
319 | if (g->scale_profile) | 319 | if (g->scale_profile) |
320 | return; | 320 | return; |
321 | 321 | ||
322 | if (!platform->devfreq_governor && !platform->qos_notify) | ||
323 | return; | ||
324 | |||
322 | profile = kzalloc(sizeof(*profile), GFP_KERNEL); | 325 | profile = kzalloc(sizeof(*profile), GFP_KERNEL); |
323 | 326 | ||
324 | profile->dev = dev; | 327 | profile->dev = dev; |