diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/therm_gk20a.c | 3 |
7 files changed, 10 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 3c6d8924..32c95e2f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -442,9 +442,7 @@ done: | |||
442 | 442 | ||
443 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) | 443 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) |
444 | { | 444 | { |
445 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 445 | if (g->is_fmodel) |
446 | |||
447 | if (platform->is_fmodel) | ||
448 | return gr_gk20a_init_ctx_vars_sim(g, gr); | 446 | return gr_gk20a_init_ctx_vars_sim(g, gr); |
449 | else | 447 | else |
450 | return gr_gk20a_init_ctx_vars_fw(g, gr); | 448 | return gr_gk20a_init_ctx_vars_fw(g, gr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0e787356..22093a34 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -380,10 +380,9 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | |||
380 | { | 380 | { |
381 | u32 val; | 381 | u32 val; |
382 | u32 delay = expect_delay; | 382 | u32 delay = expect_delay; |
383 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
384 | struct nvgpu_timeout timeout; | 383 | struct nvgpu_timeout timeout; |
385 | 384 | ||
386 | if (platform->is_fmodel) | 385 | if (g->is_fmodel) |
387 | return 0; | 386 | return 0; |
388 | 387 | ||
389 | gk20a_dbg_fn(""); | 388 | gk20a_dbg_fn(""); |
@@ -1581,7 +1580,6 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1581 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 1580 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
1582 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 1581 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
1583 | u32 last_method_data = 0; | 1582 | u32 last_method_data = 0; |
1584 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1585 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 1583 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
1586 | struct nvgpu_mem *ctxheader = &ctx->mem; | 1584 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1587 | 1585 | ||
@@ -1595,7 +1593,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1595 | if (gr->ctx_vars.golden_image_initialized) { | 1593 | if (gr->ctx_vars.golden_image_initialized) { |
1596 | goto clean_up; | 1594 | goto clean_up; |
1597 | } | 1595 | } |
1598 | if (!platform->is_fmodel) { | 1596 | if (!g->is_fmodel) { |
1599 | struct nvgpu_timeout timeout; | 1597 | struct nvgpu_timeout timeout; |
1600 | 1598 | ||
1601 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1599 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, |
@@ -1638,7 +1636,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1638 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1636 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1639 | nvgpu_udelay(10); | 1637 | nvgpu_udelay(10); |
1640 | 1638 | ||
1641 | if (!platform->is_fmodel) { | 1639 | if (!g->is_fmodel) { |
1642 | struct nvgpu_timeout timeout; | 1640 | struct nvgpu_timeout timeout; |
1643 | 1641 | ||
1644 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1642 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, |
@@ -2580,11 +2578,10 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g) | |||
2580 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | 2578 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) |
2581 | { | 2579 | { |
2582 | int err; | 2580 | int err; |
2583 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
2584 | 2581 | ||
2585 | gk20a_dbg_fn(""); | 2582 | gk20a_dbg_fn(""); |
2586 | 2583 | ||
2587 | if (platform->is_fmodel) { | 2584 | if (g->is_fmodel) { |
2588 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 2585 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
2589 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 2586 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
2590 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 2587 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 6162d420..b92dda6d 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c | |||
@@ -91,9 +91,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
91 | u64 compbit_base_post_multiply64; | 91 | u64 compbit_base_post_multiply64; |
92 | u64 compbit_store_iova; | 92 | u64 compbit_store_iova; |
93 | u64 compbit_base_post_divide64; | 93 | u64 compbit_base_post_divide64; |
94 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
95 | 94 | ||
96 | if (platform->is_fmodel) | 95 | if (g->is_fmodel) |
97 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | 96 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); |
98 | else | 97 | else |
99 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | 98 | compbit_store_iova = g->ops.mm.get_iova_addr(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index d8d9226c..4bd8f816 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -49,7 +49,6 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
49 | u32 compbit_backing_size; | 49 | u32 compbit_backing_size; |
50 | 50 | ||
51 | int err; | 51 | int err; |
52 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
53 | 52 | ||
54 | gk20a_dbg_fn(""); | 53 | gk20a_dbg_fn(""); |
55 | 54 | ||
@@ -83,7 +82,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
83 | gk20a_dbg_info("max comptag lines : %d", | 82 | gk20a_dbg_info("max comptag lines : %d", |
84 | max_comptag_lines); | 83 | max_comptag_lines); |
85 | 84 | ||
86 | if (platform->is_fmodel) | 85 | if (g->is_fmodel) |
87 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 86 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
88 | else | 87 | else |
89 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 88 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index 4bdbda43..1115a5fb 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h | |||
@@ -39,9 +39,6 @@ struct gk20a_platform { | |||
39 | struct gk20a *g; | 39 | struct gk20a *g; |
40 | 40 | ||
41 | /* Should be populated at probe. */ | 41 | /* Should be populated at probe. */ |
42 | bool is_fmodel; | ||
43 | |||
44 | /* Should be populated at probe. */ | ||
45 | bool can_railgate; | 42 | bool can_railgate; |
46 | 43 | ||
47 | /* Set by User while disabling railgating */ | 44 | /* Set by User while disabling railgating */ |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 07cdc9e5..1584ffda 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -28,9 +28,7 @@ | |||
28 | 28 | ||
29 | void gk20a_enable_priv_ring(struct gk20a *g) | 29 | void gk20a_enable_priv_ring(struct gk20a *g) |
30 | { | 30 | { |
31 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 31 | if (g->is_fmodel) |
32 | |||
33 | if (platform->is_fmodel) | ||
34 | return; | 32 | return; |
35 | 33 | ||
36 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) | 34 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) |
@@ -75,9 +73,8 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
75 | s32 retry = 100; | 73 | s32 retry = 100; |
76 | u32 gpc; | 74 | u32 gpc; |
77 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 75 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
78 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
79 | 76 | ||
80 | if (platform->is_fmodel) | 77 | if (g->is_fmodel) |
81 | return; | 78 | return; |
82 | 79 | ||
83 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c index 234c2937..0d2f1281 100644 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c | |||
@@ -117,7 +117,6 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g) | |||
117 | u32 engine_id; | 117 | u32 engine_id; |
118 | u32 active_engine_id = 0; | 118 | u32 active_engine_id = 0; |
119 | struct fifo_gk20a *f = &g->fifo; | 119 | struct fifo_gk20a *f = &g->fifo; |
120 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
121 | 120 | ||
122 | gk20a_dbg_fn(""); | 121 | gk20a_dbg_fn(""); |
123 | 122 | ||
@@ -125,7 +124,7 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g) | |||
125 | active_engine_id = f->active_engines_list[engine_id]; | 124 | active_engine_id = f->active_engines_list[engine_id]; |
126 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); | 125 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); |
127 | 126 | ||
128 | if (platform->is_fmodel) { | 127 | if (g->is_fmodel) { |
129 | gate_ctrl = set_field(gate_ctrl, | 128 | gate_ctrl = set_field(gate_ctrl, |
130 | therm_gate_ctrl_eng_delay_after_m(), | 129 | therm_gate_ctrl_eng_delay_after_m(), |
131 | therm_gate_ctrl_eng_delay_after_f(4)); | 130 | therm_gate_ctrl_eng_delay_after_f(4)); |