summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c5
-rw-r--r--drivers/gpu/nvgpu/gk20a/pramin_gk20a.c4
2 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 0def724d..5bd4dc57 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -867,6 +867,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
867 struct fifo_gk20a *f = &g->fifo; 867 struct fifo_gk20a *f = &g->fifo;
868 unsigned int chid, i; 868 unsigned int chid, i;
869 int err = 0; 869 int err = 0;
870 u64 userd_base;
870 871
871 gk20a_dbg_fn(""); 872 gk20a_dbg_fn("");
872 873
@@ -929,9 +930,9 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
929 } 930 }
930 gk20a_dbg(gpu_dbg_map, "userd gpu va = 0x%llx", f->userd.gpu_va); 931 gk20a_dbg(gpu_dbg_map, "userd gpu va = 0x%llx", f->userd.gpu_va);
931 932
933 userd_base = nvgpu_mem_get_addr(g, &f->userd);
932 for (chid = 0; chid < f->num_channels; chid++) { 934 for (chid = 0; chid < f->num_channels; chid++) {
933 f->channel[chid].userd_iova = 935 f->channel[chid].userd_iova = userd_base +
934 nvgpu_mem_get_addr(g, &f->userd) +
935 chid * f->userd_entry_size; 936 chid * f->userd_entry_size;
936 f->channel[chid].userd_gpu_va = 937 f->channel[chid].userd_gpu_va =
937 f->userd.gpu_va + chid * f->userd_entry_size; 938 f->userd.gpu_va + chid * f->userd_entry_size;
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
index 67fd2480..a76e2580 100644
--- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
@@ -34,7 +34,7 @@
34u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem, 34u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
35 struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w) 35 struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w)
36{ 36{
37 u64 bufbase = nvgpu_sgt_get_phys(sgt, sgl); 37 u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl);
38 u64 addr = bufbase + w * sizeof(u32); 38 u64 addr = bufbase + w * sizeof(u32);
39 u32 hi = (u32)((addr & ~(u64)0xfffff) 39 u32 hi = (u32)((addr & ~(u64)0xfffff)
40 >> bus_bar0_window_target_bar0_window_base_shift_v()); 40 >> bus_bar0_window_target_bar0_window_base_shift_v());
@@ -48,7 +48,7 @@ u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
48 gk20a_dbg(gpu_dbg_mem, 48 gk20a_dbg(gpu_dbg_mem,
49 "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)", 49 "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)",
50 hi, lo, mem, sgl, bufbase, 50 hi, lo, mem, sgl, bufbase,
51 bufbase + nvgpu_sgt_get_phys(sgt, sgl), 51 bufbase + nvgpu_sgt_get_phys(g, sgt, sgl),
52 nvgpu_sgt_get_length(sgt, sgl)); 52 nvgpu_sgt_get_length(sgt, sgl));
53 53
54 WARN_ON(!bufbase); 54 WARN_ON(!bufbase);