diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 4 |
2 files changed, 6 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 629a22ef..11de11de 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -459,7 +459,7 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set) | |||
459 | pwr_pmu_msgq_tail_val_f(*tail)); | 459 | pwr_pmu_msgq_tail_val_f(*tail)); |
460 | } | 460 | } |
461 | 461 | ||
462 | static int gk20a_init_pmu_setup_hw1(struct gk20a *g) | 462 | int gk20a_init_pmu_setup_hw1(struct gk20a *g) |
463 | { | 463 | { |
464 | struct nvgpu_pmu *pmu = &g->pmu; | 464 | struct nvgpu_pmu *pmu = &g->pmu; |
465 | int err = 0; | 465 | int err = 0; |
@@ -493,7 +493,7 @@ static int gk20a_init_pmu_setup_hw1(struct gk20a *g) | |||
493 | 493 | ||
494 | } | 494 | } |
495 | 495 | ||
496 | static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | 496 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) |
497 | { | 497 | { |
498 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | 498 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); |
499 | } | 499 | } |
@@ -521,7 +521,7 @@ int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) | |||
521 | return 0; | 521 | return 0; |
522 | } | 522 | } |
523 | 523 | ||
524 | static bool gk20a_is_pmu_supported(struct gk20a *g) | 524 | bool gk20a_is_pmu_supported(struct gk20a *g) |
525 | { | 525 | { |
526 | return true; | 526 | return true; |
527 | } | 527 | } |
@@ -539,45 +539,6 @@ u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) | |||
539 | return 0; | 539 | return 0; |
540 | } | 540 | } |
541 | 541 | ||
542 | void gk20a_init_pmu_ops(struct gpu_ops *gops) | ||
543 | { | ||
544 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; | ||
545 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; | ||
546 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; | ||
547 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap; | ||
548 | gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; | ||
549 | gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; | ||
550 | gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; | ||
551 | gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; | ||
552 | gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; | ||
553 | gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; | ||
554 | gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; | ||
555 | gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; | ||
556 | gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; | ||
557 | gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; | ||
558 | gops->pmu.pmu_setup_elpg = NULL; | ||
559 | gops->pmu.init_wpr_region = NULL; | ||
560 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
561 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; | ||
562 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | ||
563 | gops->pmu.pmu_pg_init_param = NULL; | ||
564 | gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; | ||
565 | gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; | ||
566 | gops->pmu.pmu_is_lpwr_feature_supported = NULL; | ||
567 | gops->pmu.pmu_lpwr_enable_pg = NULL; | ||
568 | gops->pmu.pmu_lpwr_disable_pg = NULL; | ||
569 | gops->pmu.pmu_pg_param_post_init = NULL; | ||
570 | gops->pmu.dump_secure_fuses = NULL; | ||
571 | gops->pmu.is_lazy_bootstrap = NULL; | ||
572 | gops->pmu.is_priv_load = NULL; | ||
573 | gops->pmu.get_wpr = NULL; | ||
574 | gops->pmu.alloc_blob_space = NULL; | ||
575 | gops->pmu.pmu_populate_loader_cfg = NULL; | ||
576 | gops->pmu.flcn_populate_bl_dmem_desc = NULL; | ||
577 | gops->pmu.reset_engine = gk20a_pmu_engine_reset; | ||
578 | gops->pmu.is_engine_in_reset = gk20a_pmu_is_engine_in_reset; | ||
579 | } | ||
580 | |||
581 | static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, | 542 | static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, |
582 | void *param, u32 handle, u32 status) | 543 | void *param, u32 handle, u32 status) |
583 | { | 544 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 997a88d2..f4e8c601 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -54,7 +54,9 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set); | |||
54 | u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id); | 54 | u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id); |
55 | void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); | 55 | void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); |
56 | 56 | ||
57 | void gk20a_init_pmu_ops(struct gpu_ops *gops); | 57 | int gk20a_init_pmu_setup_hw1(struct gk20a *g); |
58 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr); | ||
59 | bool gk20a_is_pmu_supported(struct gk20a *g); | ||
58 | 60 | ||
59 | void pmu_copy_to_dmem(struct nvgpu_pmu *pmu, | 61 | void pmu_copy_to_dmem(struct nvgpu_pmu *pmu, |
60 | u32 dst, u8 *src, u32 size, u8 port); | 62 | u32 dst, u8 *src, u32 size, u8 port); |