diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 9 |
3 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8efb009a..ead1f69e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -41,6 +41,7 @@ struct nvgpu_clk_pll_debug_data; | |||
41 | struct nvgpu_nvhost_dev; | 41 | struct nvgpu_nvhost_dev; |
42 | struct nvgpu_cpu_time_correlation_sample; | 42 | struct nvgpu_cpu_time_correlation_sample; |
43 | struct nvgpu_mem_sgt; | 43 | struct nvgpu_mem_sgt; |
44 | struct nvgpu_warpstate; | ||
44 | 45 | ||
45 | #include <nvgpu/lock.h> | 46 | #include <nvgpu/lock.h> |
46 | #include <nvgpu/thread.h> | 47 | #include <nvgpu/thread.h> |
@@ -308,7 +309,7 @@ struct gpu_ops { | |||
308 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, | 309 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, |
309 | u64 sms, bool enable); | 310 | u64 sms, bool enable); |
310 | void (*bpt_reg_info)(struct gk20a *g, | 311 | void (*bpt_reg_info)(struct gk20a *g, |
311 | struct warpstate *w_state); | 312 | struct nvgpu_warpstate *w_state); |
312 | void (*get_access_map)(struct gk20a *g, | 313 | void (*get_access_map)(struct gk20a *g, |
313 | u32 **whitelist, int *num_entries); | 314 | u32 **whitelist, int *num_entries); |
314 | int (*handle_fecs_error)(struct gk20a *g, | 315 | int (*handle_fecs_error)(struct gk20a *g, |
@@ -407,7 +408,7 @@ struct gpu_ops { | |||
407 | void (*load_tpc_mask)(struct gk20a *g); | 408 | void (*load_tpc_mask)(struct gk20a *g); |
408 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); | 409 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); |
409 | int (*trigger_suspend)(struct gk20a *g); | 410 | int (*trigger_suspend)(struct gk20a *g); |
410 | int (*wait_for_pause)(struct gk20a *g, struct warpstate *w_state); | 411 | int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state); |
411 | int (*resume_from_pause)(struct gk20a *g); | 412 | int (*resume_from_pause)(struct gk20a *g); |
412 | int (*clear_sm_errors)(struct gk20a *g); | 413 | int (*clear_sm_errors)(struct gk20a *g); |
413 | u32 (*tpc_enabled_exceptions)(struct gk20a *g); | 414 | u32 (*tpc_enabled_exceptions)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6f829282..1ade6b6a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8488,7 +8488,7 @@ int gr_gk20a_trigger_suspend(struct gk20a *g) | |||
8488 | return err; | 8488 | return err; |
8489 | } | 8489 | } |
8490 | 8490 | ||
8491 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state) | 8491 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state) |
8492 | { | 8492 | { |
8493 | int err = 0; | 8493 | int err = 0; |
8494 | struct gr_gk20a *gr = &g->gr; | 8494 | struct gr_gk20a *gr = &g->gr; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index a78f0498..5fab43ca 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -51,6 +51,7 @@ | |||
51 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ | 51 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ |
52 | 52 | ||
53 | struct channel_gk20a; | 53 | struct channel_gk20a; |
54 | struct nvgpu_warpstate; | ||
54 | 55 | ||
55 | enum /* global_ctx_buffer */ { | 56 | enum /* global_ctx_buffer */ { |
56 | CIRCULAR = 0, | 57 | CIRCULAR = 0, |
@@ -488,6 +489,12 @@ struct fecs_method_op_gk20a { | |||
488 | 489 | ||
489 | }; | 490 | }; |
490 | 491 | ||
492 | struct nvgpu_warpstate { | ||
493 | u64 valid_warps[2]; | ||
494 | u64 trapped_warps[2]; | ||
495 | u64 paused_warps[2]; | ||
496 | }; | ||
497 | |||
491 | struct gpu_ops; | 498 | struct gpu_ops; |
492 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | 499 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, |
493 | struct channel_gk20a *c); | 500 | struct channel_gk20a *c); |
@@ -718,7 +725,7 @@ void gk20a_gr_enable_gpc_exceptions(struct gk20a *g); | |||
718 | void gk20a_gr_enable_exceptions(struct gk20a *g); | 725 | void gk20a_gr_enable_exceptions(struct gk20a *g); |
719 | int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); | 726 | int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); |
720 | int gr_gk20a_trigger_suspend(struct gk20a *g); | 727 | int gr_gk20a_trigger_suspend(struct gk20a *g); |
721 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state); | 728 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state); |
722 | int gr_gk20a_resume_from_pause(struct gk20a *g); | 729 | int gr_gk20a_resume_from_pause(struct gk20a *g); |
723 | int gr_gk20a_clear_sm_errors(struct gk20a *g); | 730 | int gr_gk20a_clear_sm_errors(struct gk20a *g); |
724 | u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); | 731 | u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); |