diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 4 |
3 files changed, 18 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 380c28ac..a0753770 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <nvgpu/soc.h> | 25 | #include <nvgpu/soc.h> |
26 | #include <nvgpu/enabled.h> | 26 | #include <nvgpu/enabled.h> |
27 | #include <nvgpu/pmu.h> | 27 | #include <nvgpu/pmu.h> |
28 | #include <nvgpu/gmmu.h> | ||
28 | 29 | ||
29 | #include <trace/events/gk20a.h> | 30 | #include <trace/events/gk20a.h> |
30 | 31 | ||
@@ -174,6 +175,14 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
174 | g->gpu_reset_done = true; | 175 | g->gpu_reset_done = true; |
175 | } | 176 | } |
176 | 177 | ||
178 | /* | ||
179 | * Do this early so any early VMs that get made are capable of mapping | ||
180 | * buffers. | ||
181 | */ | ||
182 | err = nvgpu_pd_cache_init(g); | ||
183 | if (err) | ||
184 | return err; | ||
185 | |||
177 | /* init interface layer support for PMU falcon */ | 186 | /* init interface layer support for PMU falcon */ |
178 | nvgpu_flcn_sw_init(g, FALCON_ID_PMU); | 187 | nvgpu_flcn_sw_init(g, FALCON_ID_PMU); |
179 | nvgpu_flcn_sw_init(g, FALCON_ID_SEC2); | 188 | nvgpu_flcn_sw_init(g, FALCON_ID_SEC2); |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 558a1b06..0a84cabb 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -478,6 +478,7 @@ static void gk20a_remove_mm_support(struct mm_gk20a *mm) | |||
478 | 478 | ||
479 | gk20a_semaphore_sea_destroy(g); | 479 | gk20a_semaphore_sea_destroy(g); |
480 | gk20a_vidmem_destroy(g); | 480 | gk20a_vidmem_destroy(g); |
481 | nvgpu_pd_cache_fini(g); | ||
481 | } | 482 | } |
482 | 483 | ||
483 | static int gk20a_alloc_sysmem_flush(struct gk20a *g) | 484 | static int gk20a_alloc_sysmem_flush(struct gk20a *g) |
@@ -1560,7 +1561,7 @@ static inline u32 big_valid_pde0_bits(struct gk20a *g, | |||
1560 | struct nvgpu_gmmu_pd *pd, u64 addr) | 1561 | struct nvgpu_gmmu_pd *pd, u64 addr) |
1561 | { | 1562 | { |
1562 | u32 pde0_bits = | 1563 | u32 pde0_bits = |
1563 | nvgpu_aperture_mask(g, &pd->mem, | 1564 | nvgpu_aperture_mask(g, pd->mem, |
1564 | gmmu_pde_aperture_big_sys_mem_ncoh_f(), | 1565 | gmmu_pde_aperture_big_sys_mem_ncoh_f(), |
1565 | gmmu_pde_aperture_big_video_memory_f()) | | 1566 | gmmu_pde_aperture_big_video_memory_f()) | |
1566 | gmmu_pde_address_big_sys_f( | 1567 | gmmu_pde_address_big_sys_f( |
@@ -1573,7 +1574,7 @@ static inline u32 small_valid_pde1_bits(struct gk20a *g, | |||
1573 | struct nvgpu_gmmu_pd *pd, u64 addr) | 1574 | struct nvgpu_gmmu_pd *pd, u64 addr) |
1574 | { | 1575 | { |
1575 | u32 pde1_bits = | 1576 | u32 pde1_bits = |
1576 | nvgpu_aperture_mask(g, &pd->mem, | 1577 | nvgpu_aperture_mask(g, pd->mem, |
1577 | gmmu_pde_aperture_small_sys_mem_ncoh_f(), | 1578 | gmmu_pde_aperture_small_sys_mem_ncoh_f(), |
1578 | gmmu_pde_aperture_small_video_memory_f()) | | 1579 | gmmu_pde_aperture_small_video_memory_f()) | |
1579 | gmmu_pde_vol_small_true_f() | /* tbd: why? */ | 1580 | gmmu_pde_vol_small_true_f() | /* tbd: why? */ |
@@ -2173,14 +2174,14 @@ static int gk20a_init_ce_vm(struct mm_gk20a *mm) | |||
2173 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 2174 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
2174 | struct vm_gk20a *vm) | 2175 | struct vm_gk20a *vm) |
2175 | { | 2176 | { |
2176 | u64 pdb_addr = nvgpu_mem_get_base_addr(g, &vm->pdb.mem, 0); | 2177 | u64 pdb_addr = nvgpu_mem_get_base_addr(g, vm->pdb.mem, 0); |
2177 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 2178 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
2178 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 2179 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
2179 | 2180 | ||
2180 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); | 2181 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); |
2181 | 2182 | ||
2182 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), | 2183 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), |
2183 | nvgpu_aperture_mask(g, &vm->pdb.mem, | 2184 | nvgpu_aperture_mask(g, vm->pdb.mem, |
2184 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), | 2185 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), |
2185 | ram_in_page_dir_base_target_vid_mem_f()) | | 2186 | ram_in_page_dir_base_target_vid_mem_f()) | |
2186 | ram_in_page_dir_base_vol_true_f() | | 2187 | ram_in_page_dir_base_vol_true_f() | |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index a245d0e0..cadcffa4 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -31,6 +31,8 @@ | |||
31 | #include <nvgpu/rbtree.h> | 31 | #include <nvgpu/rbtree.h> |
32 | #include <nvgpu/kref.h> | 32 | #include <nvgpu/kref.h> |
33 | 33 | ||
34 | struct nvgpu_pd_cache; | ||
35 | |||
34 | #ifdef CONFIG_ARM64 | 36 | #ifdef CONFIG_ARM64 |
35 | #define outer_flush_range(a, b) | 37 | #define outer_flush_range(a, b) |
36 | #define __cpuc_flush_dcache_area __flush_dcache_area | 38 | #define __cpuc_flush_dcache_area __flush_dcache_area |
@@ -217,6 +219,8 @@ struct mm_gk20a { | |||
217 | struct vm_gk20a *vm; | 219 | struct vm_gk20a *vm; |
218 | } ce; | 220 | } ce; |
219 | 221 | ||
222 | struct nvgpu_pd_cache *pd_cache; | ||
223 | |||
220 | struct nvgpu_mutex l2_op_lock; | 224 | struct nvgpu_mutex l2_op_lock; |
221 | struct nvgpu_mutex tlb_lock; | 225 | struct nvgpu_mutex tlb_lock; |
222 | struct nvgpu_mutex priv_lock; | 226 | struct nvgpu_mutex priv_lock; |