diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 327 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 345 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.h | 24 |
5 files changed, 354 insertions, 346 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 1d6fb0e9..0b53bffc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -18,7 +18,6 @@ | |||
18 | 18 | ||
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <linux/dma-mapping.h> | 20 | #include <linux/dma-mapping.h> |
21 | #include <linux/highmem.h> | ||
22 | #include <linux/string.h> | 21 | #include <linux/string.h> |
23 | #include <linux/cdev.h> | 22 | #include <linux/cdev.h> |
24 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
@@ -73,7 +72,6 @@ | |||
73 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 72 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
74 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> | 73 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> |
75 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> | 74 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> |
76 | #include <nvgpu/hw/gk20a/hw_sim_gk20a.h> | ||
77 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 75 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
78 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 76 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
79 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 77 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
@@ -276,16 +274,6 @@ void __nvgpu_check_gpu_state(struct gk20a *g) | |||
276 | } | 274 | } |
277 | } | 275 | } |
278 | 276 | ||
279 | static inline void sim_writel(struct gk20a *g, u32 r, u32 v) | ||
280 | { | ||
281 | writel(v, g->sim.regs+r); | ||
282 | } | ||
283 | |||
284 | static inline u32 sim_readl(struct gk20a *g, u32 r) | ||
285 | { | ||
286 | return readl(g->sim.regs+r); | ||
287 | } | ||
288 | |||
289 | /* | 277 | /* |
290 | * Locks out the driver from accessing GPU registers. This prevents access to | 278 | * Locks out the driver from accessing GPU registers. This prevents access to |
291 | * thse registers after the GPU has been clock or power gated. This should help | 279 | * thse registers after the GPU has been clock or power gated. This should help |
@@ -317,69 +305,7 @@ void __gk20a_warn_on_no_regs(void) | |||
317 | WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); | 305 | WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); |
318 | } | 306 | } |
319 | 307 | ||
320 | static void kunmap_and_free_iopage(void **kvaddr, struct page **page) | 308 | void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, |
321 | { | ||
322 | if (*kvaddr) { | ||
323 | kunmap(*kvaddr); | ||
324 | *kvaddr = NULL; | ||
325 | } | ||
326 | if (*page) { | ||
327 | __free_page(*page); | ||
328 | *page = NULL; | ||
329 | } | ||
330 | } | ||
331 | |||
332 | static void gk20a_free_sim_support(struct gk20a *g) | ||
333 | { | ||
334 | /* free sim mappings, bfrs */ | ||
335 | kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, | ||
336 | &g->sim.send_bfr.page); | ||
337 | |||
338 | kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, | ||
339 | &g->sim.recv_bfr.page); | ||
340 | |||
341 | kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, | ||
342 | &g->sim.msg_bfr.page); | ||
343 | } | ||
344 | |||
345 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | ||
346 | { | ||
347 | struct gk20a *g = s->g; | ||
348 | if (g->sim.regs) | ||
349 | sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); | ||
350 | gk20a_free_sim_support(g); | ||
351 | } | ||
352 | |||
353 | static int alloc_and_kmap_iopage(struct device *d, | ||
354 | void **kvaddr, | ||
355 | u64 *phys, | ||
356 | struct page **page) | ||
357 | { | ||
358 | int err = 0; | ||
359 | *page = alloc_page(GFP_KERNEL); | ||
360 | |||
361 | if (!*page) { | ||
362 | err = -ENOMEM; | ||
363 | dev_err(d, "couldn't allocate io page\n"); | ||
364 | goto fail; | ||
365 | } | ||
366 | |||
367 | *kvaddr = kmap(*page); | ||
368 | if (!*kvaddr) { | ||
369 | err = -ENOMEM; | ||
370 | dev_err(d, "couldn't kmap io page\n"); | ||
371 | goto fail; | ||
372 | } | ||
373 | *phys = page_to_phys(*page); | ||
374 | return 0; | ||
375 | |||
376 | fail: | ||
377 | kunmap_and_free_iopage(kvaddr, page); | ||
378 | return err; | ||
379 | |||
380 | } | ||
381 | |||
382 | static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, | ||
383 | struct resource **out) | 309 | struct resource **out) |
384 | { | 310 | { |
385 | struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i); | 311 | struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i); |
@@ -390,257 +316,6 @@ static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, | |||
390 | return devm_ioremap_resource(&dev->dev, r); | 316 | return devm_ioremap_resource(&dev->dev, r); |
391 | } | 317 | } |
392 | 318 | ||
393 | /* TBD: strip from released */ | ||
394 | static int gk20a_init_sim_support(struct platform_device *pdev) | ||
395 | { | ||
396 | int err = 0; | ||
397 | struct device *dev = &pdev->dev; | ||
398 | struct gk20a *g = get_gk20a(dev); | ||
399 | u64 phys; | ||
400 | |||
401 | g->sim.g = g; | ||
402 | g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM, | ||
403 | &g->sim.reg_mem); | ||
404 | if (IS_ERR(g->sim.regs)) { | ||
405 | dev_err(dev, "failed to remap gk20a sim regs\n"); | ||
406 | err = PTR_ERR(g->sim.regs); | ||
407 | goto fail; | ||
408 | } | ||
409 | |||
410 | /* allocate sim event/msg buffers */ | ||
411 | err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr, | ||
412 | &g->sim.send_bfr.phys, | ||
413 | &g->sim.send_bfr.page); | ||
414 | |||
415 | err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr, | ||
416 | &g->sim.recv_bfr.phys, | ||
417 | &g->sim.recv_bfr.page); | ||
418 | |||
419 | err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr, | ||
420 | &g->sim.msg_bfr.phys, | ||
421 | &g->sim.msg_bfr.page); | ||
422 | |||
423 | if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && | ||
424 | g->sim.msg_bfr.kvaddr)) { | ||
425 | dev_err(dev, "couldn't allocate all sim buffers\n"); | ||
426 | goto fail; | ||
427 | } | ||
428 | |||
429 | /*mark send ring invalid*/ | ||
430 | sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); | ||
431 | |||
432 | /*read get pointer and make equal to put*/ | ||
433 | g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); | ||
434 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
435 | |||
436 | /*write send ring address and make it valid*/ | ||
437 | phys = g->sim.send_bfr.phys; | ||
438 | sim_writel(g, sim_send_ring_hi_r(), | ||
439 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | ||
440 | sim_writel(g, sim_send_ring_r(), | ||
441 | sim_send_ring_status_valid_f() | | ||
442 | sim_send_ring_target_phys_pci_coherent_f() | | ||
443 | sim_send_ring_size_4kb_f() | | ||
444 | sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
445 | |||
446 | /*repeat for recv ring (but swap put,get as roles are opposite) */ | ||
447 | sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); | ||
448 | |||
449 | /*read put pointer and make equal to get*/ | ||
450 | g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); | ||
451 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
452 | |||
453 | /*write send ring address and make it valid*/ | ||
454 | phys = g->sim.recv_bfr.phys; | ||
455 | sim_writel(g, sim_recv_ring_hi_r(), | ||
456 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | ||
457 | sim_writel(g, sim_recv_ring_r(), | ||
458 | sim_recv_ring_status_valid_f() | | ||
459 | sim_recv_ring_target_phys_pci_coherent_f() | | ||
460 | sim_recv_ring_size_4kb_f() | | ||
461 | sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
462 | |||
463 | g->sim.remove_support = gk20a_remove_sim_support; | ||
464 | return 0; | ||
465 | |||
466 | fail: | ||
467 | gk20a_free_sim_support(g); | ||
468 | return err; | ||
469 | } | ||
470 | |||
471 | static inline u32 sim_msg_header_size(void) | ||
472 | { | ||
473 | return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ | ||
474 | } | ||
475 | |||
476 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | ||
477 | { | ||
478 | return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); | ||
479 | } | ||
480 | |||
481 | static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) | ||
482 | { | ||
483 | return sim_msg_bfr(g, byte_offset); /*starts at 0*/ | ||
484 | } | ||
485 | |||
486 | static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) | ||
487 | { | ||
488 | /*starts after msg header/cmn*/ | ||
489 | return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); | ||
490 | } | ||
491 | |||
492 | static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) | ||
493 | { | ||
494 | /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ | ||
495 | *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); | ||
496 | *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); | ||
497 | *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); | ||
498 | *sim_msg_hdr(g, sim_msg_function_r()) = func; | ||
499 | *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); | ||
500 | } | ||
501 | |||
502 | static inline u32 sim_escape_read_hdr_size(void) | ||
503 | { | ||
504 | return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ | ||
505 | } | ||
506 | |||
507 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
508 | { | ||
509 | return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); | ||
510 | } | ||
511 | |||
512 | static int rpc_send_message(struct gk20a *g) | ||
513 | { | ||
514 | /* calculations done in units of u32s */ | ||
515 | u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; | ||
516 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | ||
517 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | ||
518 | |||
519 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | ||
520 | sim_dma_target_phys_pci_coherent_f() | | ||
521 | sim_dma_status_valid_f() | | ||
522 | sim_dma_size_4kb_f() | | ||
523 | sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); | ||
524 | |||
525 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | ||
526 | u64_hi32(g->sim.msg_bfr.phys); | ||
527 | |||
528 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; | ||
529 | |||
530 | g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % | ||
531 | PAGE_SIZE; | ||
532 | |||
533 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
534 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
535 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
536 | |||
537 | /* Update the put pointer. This will trap into the host. */ | ||
538 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
539 | |||
540 | return 0; | ||
541 | } | ||
542 | |||
543 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
544 | { | ||
545 | return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); | ||
546 | } | ||
547 | |||
548 | static int rpc_recv_poll(struct gk20a *g) | ||
549 | { | ||
550 | u64 recv_phys_addr; | ||
551 | |||
552 | /* XXX This read is not required (?) */ | ||
553 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | ||
554 | |||
555 | /* Poll the recv ring get pointer in an infinite loop*/ | ||
556 | do { | ||
557 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
558 | } while (g->sim.recv_ring_put == g->sim.recv_ring_get); | ||
559 | |||
560 | /* process all replies */ | ||
561 | while (g->sim.recv_ring_put != g->sim.recv_ring_get) { | ||
562 | /* these are in u32 offsets*/ | ||
563 | u32 dma_lo_offset = | ||
564 | sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; | ||
565 | u32 dma_hi_offset = dma_lo_offset + 1; | ||
566 | u32 recv_phys_addr_lo = sim_dma_addr_lo_v( | ||
567 | *sim_recv_ring_bfr(g, dma_lo_offset*4)); | ||
568 | u32 recv_phys_addr_hi = sim_dma_hi_addr_v( | ||
569 | *sim_recv_ring_bfr(g, dma_hi_offset*4)); | ||
570 | |||
571 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | ||
572 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | ||
573 | |||
574 | if (recv_phys_addr != g->sim.msg_bfr.phys) { | ||
575 | dev_err(dev_from_gk20a(g), "%s Error in RPC reply\n", | ||
576 | __func__); | ||
577 | return -1; | ||
578 | } | ||
579 | |||
580 | /* Update GET pointer */ | ||
581 | g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % | ||
582 | PAGE_SIZE; | ||
583 | |||
584 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
585 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
586 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
587 | |||
588 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
589 | |||
590 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
591 | } | ||
592 | |||
593 | return 0; | ||
594 | } | ||
595 | |||
596 | static int issue_rpc_and_wait(struct gk20a *g) | ||
597 | { | ||
598 | int err; | ||
599 | |||
600 | err = rpc_send_message(g); | ||
601 | if (err) { | ||
602 | dev_err(dev_from_gk20a(g), "%s failed rpc_send_message\n", | ||
603 | __func__); | ||
604 | return err; | ||
605 | } | ||
606 | |||
607 | err = rpc_recv_poll(g); | ||
608 | if (err) { | ||
609 | dev_err(dev_from_gk20a(g), "%s failed rpc_recv_poll\n", | ||
610 | __func__); | ||
611 | return err; | ||
612 | } | ||
613 | |||
614 | /* Now check if RPC really succeeded */ | ||
615 | if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { | ||
616 | dev_err(dev_from_gk20a(g), "%s received failed status!\n", | ||
617 | __func__); | ||
618 | return -(*sim_msg_hdr(g, sim_msg_result_r())); | ||
619 | } | ||
620 | return 0; | ||
621 | } | ||
622 | |||
623 | int gk20a_sim_esc_read(struct gk20a *g, char *path, u32 index, u32 count, u32 *data) | ||
624 | { | ||
625 | int err; | ||
626 | size_t pathlen = strlen(path); | ||
627 | u32 data_offset; | ||
628 | |||
629 | sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), | ||
630 | sim_escape_read_hdr_size()); | ||
631 | *sim_msg_param(g, 0) = index; | ||
632 | *sim_msg_param(g, 4) = count; | ||
633 | data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); | ||
634 | *sim_msg_param(g, 8) = data_offset; | ||
635 | strcpy((char *)sim_msg_param(g, 0xc), path); | ||
636 | |||
637 | err = issue_rpc_and_wait(g); | ||
638 | |||
639 | if (!err) | ||
640 | memcpy(data, sim_msg_param(g, data_offset), count); | ||
641 | return err; | ||
642 | } | ||
643 | |||
644 | static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id) | 319 | static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id) |
645 | { | 320 | { |
646 | struct gk20a *g = dev_id; | 321 | struct gk20a *g = dev_id; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 95730b4e..c1e1b564 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1476,4 +1476,7 @@ int gk20a_railgating_debugfs_init(struct device *dev); | |||
1476 | #endif | 1476 | #endif |
1477 | 1477 | ||
1478 | int gk20a_secure_page_alloc(struct device *dev); | 1478 | int gk20a_secure_page_alloc(struct device *dev); |
1479 | void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, | ||
1480 | struct resource **out); | ||
1481 | |||
1479 | #endif /* GK20A_H */ | 1482 | #endif /* GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index 70787202..34b315e6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | |||
@@ -20,6 +20,7 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include "gk20a.h" | 22 | #include "gk20a.h" |
23 | #include "sim_gk20a.h" | ||
23 | #include "gr_ctx_gk20a.h" | 24 | #include "gr_ctx_gk20a.h" |
24 | 25 | ||
25 | int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | 26 | int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) |
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c new file mode 100644 index 00000000..76d29ee5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c | |||
@@ -0,0 +1,345 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/io.h> | ||
18 | #include <linux/highmem.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | |||
21 | #include "gk20a.h" | ||
22 | |||
23 | #include <nvgpu/hw/gk20a/hw_sim_gk20a.h> | ||
24 | |||
25 | static inline void sim_writel(struct gk20a *g, u32 r, u32 v) | ||
26 | { | ||
27 | writel(v, g->sim.regs + r); | ||
28 | } | ||
29 | |||
30 | static inline u32 sim_readl(struct gk20a *g, u32 r) | ||
31 | { | ||
32 | return readl(g->sim.regs + r); | ||
33 | } | ||
34 | |||
35 | static void kunmap_and_free_iopage(void **kvaddr, struct page **page) | ||
36 | { | ||
37 | if (*kvaddr) { | ||
38 | kunmap(*kvaddr); | ||
39 | *kvaddr = NULL; | ||
40 | } | ||
41 | if (*page) { | ||
42 | __free_page(*page); | ||
43 | *page = NULL; | ||
44 | } | ||
45 | } | ||
46 | |||
47 | static void gk20a_free_sim_support(struct gk20a *g) | ||
48 | { | ||
49 | /* free sim mappings, bfrs */ | ||
50 | kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, | ||
51 | &g->sim.send_bfr.page); | ||
52 | |||
53 | kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, | ||
54 | &g->sim.recv_bfr.page); | ||
55 | |||
56 | kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, | ||
57 | &g->sim.msg_bfr.page); | ||
58 | } | ||
59 | |||
60 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | ||
61 | { | ||
62 | struct gk20a *g = s->g; | ||
63 | if (g->sim.regs) | ||
64 | sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); | ||
65 | gk20a_free_sim_support(g); | ||
66 | } | ||
67 | |||
68 | static int alloc_and_kmap_iopage(struct device *d, | ||
69 | void **kvaddr, | ||
70 | u64 *phys, | ||
71 | struct page **page) | ||
72 | { | ||
73 | int err = 0; | ||
74 | *page = alloc_page(GFP_KERNEL); | ||
75 | |||
76 | if (!*page) { | ||
77 | err = -ENOMEM; | ||
78 | dev_err(d, "couldn't allocate io page\n"); | ||
79 | goto fail; | ||
80 | } | ||
81 | |||
82 | *kvaddr = kmap(*page); | ||
83 | if (!*kvaddr) { | ||
84 | err = -ENOMEM; | ||
85 | dev_err(d, "couldn't kmap io page\n"); | ||
86 | goto fail; | ||
87 | } | ||
88 | *phys = page_to_phys(*page); | ||
89 | return 0; | ||
90 | |||
91 | fail: | ||
92 | kunmap_and_free_iopage(kvaddr, page); | ||
93 | return err; | ||
94 | |||
95 | } | ||
96 | |||
97 | int gk20a_init_sim_support(struct platform_device *pdev) | ||
98 | { | ||
99 | int err = 0; | ||
100 | struct device *dev = &pdev->dev; | ||
101 | struct gk20a *g = get_gk20a(dev); | ||
102 | u64 phys; | ||
103 | |||
104 | g->sim.g = g; | ||
105 | g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM, | ||
106 | &g->sim.reg_mem); | ||
107 | if (IS_ERR(g->sim.regs)) { | ||
108 | dev_err(dev, "failed to remap gk20a sim regs\n"); | ||
109 | err = PTR_ERR(g->sim.regs); | ||
110 | goto fail; | ||
111 | } | ||
112 | |||
113 | /* allocate sim event/msg buffers */ | ||
114 | err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr, | ||
115 | &g->sim.send_bfr.phys, | ||
116 | &g->sim.send_bfr.page); | ||
117 | |||
118 | err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr, | ||
119 | &g->sim.recv_bfr.phys, | ||
120 | &g->sim.recv_bfr.page); | ||
121 | |||
122 | err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr, | ||
123 | &g->sim.msg_bfr.phys, | ||
124 | &g->sim.msg_bfr.page); | ||
125 | |||
126 | if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && | ||
127 | g->sim.msg_bfr.kvaddr)) { | ||
128 | dev_err(dev, "couldn't allocate all sim buffers\n"); | ||
129 | goto fail; | ||
130 | } | ||
131 | |||
132 | /*mark send ring invalid*/ | ||
133 | sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); | ||
134 | |||
135 | /*read get pointer and make equal to put*/ | ||
136 | g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); | ||
137 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
138 | |||
139 | /*write send ring address and make it valid*/ | ||
140 | phys = g->sim.send_bfr.phys; | ||
141 | sim_writel(g, sim_send_ring_hi_r(), | ||
142 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | ||
143 | sim_writel(g, sim_send_ring_r(), | ||
144 | sim_send_ring_status_valid_f() | | ||
145 | sim_send_ring_target_phys_pci_coherent_f() | | ||
146 | sim_send_ring_size_4kb_f() | | ||
147 | sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
148 | |||
149 | /*repeat for recv ring (but swap put,get as roles are opposite) */ | ||
150 | sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); | ||
151 | |||
152 | /*read put pointer and make equal to get*/ | ||
153 | g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); | ||
154 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
155 | |||
156 | /*write send ring address and make it valid*/ | ||
157 | phys = g->sim.recv_bfr.phys; | ||
158 | sim_writel(g, sim_recv_ring_hi_r(), | ||
159 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | ||
160 | sim_writel(g, sim_recv_ring_r(), | ||
161 | sim_recv_ring_status_valid_f() | | ||
162 | sim_recv_ring_target_phys_pci_coherent_f() | | ||
163 | sim_recv_ring_size_4kb_f() | | ||
164 | sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
165 | |||
166 | g->sim.remove_support = gk20a_remove_sim_support; | ||
167 | return 0; | ||
168 | |||
169 | fail: | ||
170 | gk20a_free_sim_support(g); | ||
171 | return err; | ||
172 | } | ||
173 | |||
174 | static inline u32 sim_msg_header_size(void) | ||
175 | { | ||
176 | return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ | ||
177 | } | ||
178 | |||
179 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | ||
180 | { | ||
181 | return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); | ||
182 | } | ||
183 | |||
184 | static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) | ||
185 | { | ||
186 | return sim_msg_bfr(g, byte_offset); /*starts at 0*/ | ||
187 | } | ||
188 | |||
189 | static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) | ||
190 | { | ||
191 | /*starts after msg header/cmn*/ | ||
192 | return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); | ||
193 | } | ||
194 | |||
195 | static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) | ||
196 | { | ||
197 | /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ | ||
198 | *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); | ||
199 | *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); | ||
200 | *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); | ||
201 | *sim_msg_hdr(g, sim_msg_function_r()) = func; | ||
202 | *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); | ||
203 | } | ||
204 | |||
205 | static inline u32 sim_escape_read_hdr_size(void) | ||
206 | { | ||
207 | return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ | ||
208 | } | ||
209 | |||
210 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
211 | { | ||
212 | return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); | ||
213 | } | ||
214 | |||
215 | static int rpc_send_message(struct gk20a *g) | ||
216 | { | ||
217 | /* calculations done in units of u32s */ | ||
218 | u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; | ||
219 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | ||
220 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | ||
221 | |||
222 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | ||
223 | sim_dma_target_phys_pci_coherent_f() | | ||
224 | sim_dma_status_valid_f() | | ||
225 | sim_dma_size_4kb_f() | | ||
226 | sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); | ||
227 | |||
228 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | ||
229 | u64_hi32(g->sim.msg_bfr.phys); | ||
230 | |||
231 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; | ||
232 | |||
233 | g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % | ||
234 | PAGE_SIZE; | ||
235 | |||
236 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
237 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
238 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
239 | |||
240 | /* Update the put pointer. This will trap into the host. */ | ||
241 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
242 | |||
243 | return 0; | ||
244 | } | ||
245 | |||
246 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
247 | { | ||
248 | return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); | ||
249 | } | ||
250 | |||
251 | static int rpc_recv_poll(struct gk20a *g) | ||
252 | { | ||
253 | u64 recv_phys_addr; | ||
254 | |||
255 | /* XXX This read is not required (?) */ | ||
256 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | ||
257 | |||
258 | /* Poll the recv ring get pointer in an infinite loop*/ | ||
259 | do { | ||
260 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
261 | } while (g->sim.recv_ring_put == g->sim.recv_ring_get); | ||
262 | |||
263 | /* process all replies */ | ||
264 | while (g->sim.recv_ring_put != g->sim.recv_ring_get) { | ||
265 | /* these are in u32 offsets*/ | ||
266 | u32 dma_lo_offset = | ||
267 | sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; | ||
268 | u32 dma_hi_offset = dma_lo_offset + 1; | ||
269 | u32 recv_phys_addr_lo = sim_dma_addr_lo_v( | ||
270 | *sim_recv_ring_bfr(g, dma_lo_offset*4)); | ||
271 | u32 recv_phys_addr_hi = sim_dma_hi_addr_v( | ||
272 | *sim_recv_ring_bfr(g, dma_hi_offset*4)); | ||
273 | |||
274 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | ||
275 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | ||
276 | |||
277 | if (recv_phys_addr != g->sim.msg_bfr.phys) { | ||
278 | dev_err(dev_from_gk20a(g), "%s Error in RPC reply\n", | ||
279 | __func__); | ||
280 | return -1; | ||
281 | } | ||
282 | |||
283 | /* Update GET pointer */ | ||
284 | g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % | ||
285 | PAGE_SIZE; | ||
286 | |||
287 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
288 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
289 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
290 | |||
291 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
292 | |||
293 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
294 | } | ||
295 | |||
296 | return 0; | ||
297 | } | ||
298 | |||
299 | static int issue_rpc_and_wait(struct gk20a *g) | ||
300 | { | ||
301 | int err; | ||
302 | |||
303 | err = rpc_send_message(g); | ||
304 | if (err) { | ||
305 | dev_err(dev_from_gk20a(g), "%s failed rpc_send_message\n", | ||
306 | __func__); | ||
307 | return err; | ||
308 | } | ||
309 | |||
310 | err = rpc_recv_poll(g); | ||
311 | if (err) { | ||
312 | dev_err(dev_from_gk20a(g), "%s failed rpc_recv_poll\n", | ||
313 | __func__); | ||
314 | return err; | ||
315 | } | ||
316 | |||
317 | /* Now check if RPC really succeeded */ | ||
318 | if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { | ||
319 | dev_err(dev_from_gk20a(g), "%s received failed status!\n", | ||
320 | __func__); | ||
321 | return -(*sim_msg_hdr(g, sim_msg_result_r())); | ||
322 | } | ||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) | ||
327 | { | ||
328 | int err; | ||
329 | size_t pathlen = strlen(path); | ||
330 | u32 data_offset; | ||
331 | |||
332 | sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), | ||
333 | sim_escape_read_hdr_size()); | ||
334 | *sim_msg_param(g, 0) = index; | ||
335 | *sim_msg_param(g, 4) = sizeof(u32); | ||
336 | data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); | ||
337 | *sim_msg_param(g, 8) = data_offset; | ||
338 | strcpy((char *)sim_msg_param(g, 0xc), path); | ||
339 | |||
340 | err = issue_rpc_and_wait(g); | ||
341 | |||
342 | if (!err) | ||
343 | memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); | ||
344 | return err; | ||
345 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h index 3c21d69e..68398b34 100644 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h | |||
@@ -21,8 +21,9 @@ | |||
21 | #ifndef __SIM_GK20A_H__ | 21 | #ifndef __SIM_GK20A_H__ |
22 | #define __SIM_GK20A_H__ | 22 | #define __SIM_GK20A_H__ |
23 | 23 | ||
24 | |||
25 | struct gk20a; | 24 | struct gk20a; |
25 | struct platform_device; | ||
26 | |||
26 | struct sim_gk20a { | 27 | struct sim_gk20a { |
27 | struct gk20a *g; | 28 | struct gk20a *g; |
28 | struct resource *reg_mem; | 29 | struct resource *reg_mem; |
@@ -39,24 +40,7 @@ struct sim_gk20a { | |||
39 | void (*remove_support)(struct sim_gk20a *); | 40 | void (*remove_support)(struct sim_gk20a *); |
40 | }; | 41 | }; |
41 | 42 | ||
42 | 43 | int gk20a_init_sim_support(struct platform_device *pdev); | |
43 | int gk20a_sim_esc_read(struct gk20a *g, char *path, u32 index, | 44 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data); |
44 | u32 count, u32 *data); | ||
45 | |||
46 | static inline int gk20a_sim_esc_read_no_sim(struct gk20a *g, char *p, | ||
47 | u32 i, u32 c, u32 *d) | ||
48 | { | ||
49 | *d = ~(u32)0; | ||
50 | return -1; | ||
51 | } | ||
52 | |||
53 | static inline int gk20a_sim_esc_readl(struct gk20a *g, char * p, u32 i, u32 *d) | ||
54 | { | ||
55 | if (tegra_cpu_is_asim()) | ||
56 | return gk20a_sim_esc_read(g, p, i, sizeof(u32), d); | ||
57 | |||
58 | return gk20a_sim_esc_read_no_sim(g, p, i, sizeof(u32), d); | ||
59 | } | ||
60 | |||
61 | 45 | ||
62 | #endif /*__SIM_GK20A_H__*/ | 46 | #endif /*__SIM_GK20A_H__*/ |