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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c5
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index e6630ebf..115cd7f4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -27,6 +27,7 @@ struct fifo_gk20a;
27struct channel_gk20a; 27struct channel_gk20a;
28struct gr_gk20a; 28struct gr_gk20a;
29struct sim_gk20a; 29struct sim_gk20a;
30struct gk20a_ctxsw_ucode_segments;
30 31
31#include <linux/sched.h> 32#include <linux/sched.h>
32#include <linux/spinlock.h> 33#include <linux/spinlock.h>
@@ -121,6 +122,10 @@ struct gpu_ops {
121 void (*set_hww_esr_report_mask)(struct gk20a *g); 122 void (*set_hww_esr_report_mask)(struct gk20a *g);
122 int (*setup_alpha_beta_tables)(struct gk20a *g, 123 int (*setup_alpha_beta_tables)(struct gk20a *g,
123 struct gr_gk20a *gr); 124 struct gr_gk20a *gr);
125 int (*falcon_load_ucode)(struct gk20a *g,
126 u64 addr_base,
127 struct gk20a_ctxsw_ucode_segments *segments,
128 u32 reg_offset);
124 } gr; 129 } gr;
125 const char *name; 130 const char *name;
126 struct { 131 struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 46a84fd6..50ca0601 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2141,10 +2141,10 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g)
2141 2141
2142 gr_gk20a_load_falcon_bind_instblk(g); 2142 gr_gk20a_load_falcon_bind_instblk(g);
2143 2143
2144 gr_gk20a_load_ctxsw_ucode_segments(g, addr_base, 2144 g->ops.gr.falcon_load_ucode(g, addr_base,
2145 &g->ctxsw_ucode_info.fecs, 0); 2145 &g->ctxsw_ucode_info.fecs, 0);
2146 2146
2147 gr_gk20a_load_ctxsw_ucode_segments(g, addr_base, 2147 g->ops.gr.falcon_load_ucode(g, addr_base,
2148 &g->ctxsw_ucode_info.gpccs, 2148 &g->ctxsw_ucode_info.gpccs,
2149 gr_gpcs_gpccs_falcon_hwcfg_r() - 2149 gr_gpcs_gpccs_falcon_hwcfg_r() -
2150 gr_fecs_falcon_hwcfg_r()); 2150 gr_fecs_falcon_hwcfg_r());
@@ -6845,4 +6845,5 @@ void gk20a_init_gr(struct gpu_ops *gops)
6845 gops->gr.init_fs_state = gr_gk20a_ctx_state_floorsweep; 6845 gops->gr.init_fs_state = gr_gk20a_ctx_state_floorsweep;
6846 gops->gr.set_hww_esr_report_mask = gr_gk20a_set_hww_esr_report_mask; 6846 gops->gr.set_hww_esr_report_mask = gr_gk20a_set_hww_esr_report_mask;
6847 gops->gr.setup_alpha_beta_tables = gr_gk20a_setup_alpha_beta_tables; 6847 gops->gr.setup_alpha_beta_tables = gr_gk20a_setup_alpha_beta_tables;
6848 gops->gr.falcon_load_ucode = gr_gk20a_load_ctxsw_ucode_segments;
6848} 6849}