diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 24 |
3 files changed, 66 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 88ce6a83..2cc5e4cd 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2671,6 +2671,21 @@ void gk20a_fifo_set_runlist_state(struct gk20a *g, u32 runlists_mask, | |||
2671 | gk20a_dbg_fn("done"); | 2671 | gk20a_dbg_fn("done"); |
2672 | } | 2672 | } |
2673 | 2673 | ||
2674 | void gk20a_fifo_enable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg) | ||
2675 | { | ||
2676 | gk20a_fifo_set_runlist_state(g, fifo_sched_disable_runlist_m( | ||
2677 | tsg->runlist_id), RUNLIST_ENABLED, | ||
2678 | !RUNLIST_INFO_MUTEX_LOCKED); | ||
2679 | |||
2680 | } | ||
2681 | |||
2682 | void gk20a_fifo_disable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg) | ||
2683 | { | ||
2684 | gk20a_fifo_set_runlist_state(g, fifo_sched_disable_runlist_m( | ||
2685 | tsg->runlist_id), RUNLIST_DISABLED, | ||
2686 | !RUNLIST_INFO_MUTEX_LOCKED); | ||
2687 | } | ||
2688 | |||
2674 | int gk20a_fifo_enable_engine_activity(struct gk20a *g, | 2689 | int gk20a_fifo_enable_engine_activity(struct gk20a *g, |
2675 | struct fifo_engine_info_gk20a *eng_info) | 2690 | struct fifo_engine_info_gk20a *eng_info) |
2676 | { | 2691 | { |
@@ -3413,6 +3428,27 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index) | |||
3413 | return pbdma_chan_eng_ctx_status_str[index]; | 3428 | return pbdma_chan_eng_ctx_status_str[index]; |
3414 | } | 3429 | } |
3415 | 3430 | ||
3431 | bool gk20a_fifo_channel_status_is_next(struct gk20a *g, u32 chid) | ||
3432 | { | ||
3433 | u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); | ||
3434 | |||
3435 | return ccsr_channel_next_v(channel) == ccsr_channel_next_true_v(); | ||
3436 | } | ||
3437 | |||
3438 | bool gk20a_fifo_channel_status_is_ctx_reload(struct gk20a *g, u32 chid) | ||
3439 | { | ||
3440 | u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); | ||
3441 | u32 status = ccsr_channel_status_v(channel); | ||
3442 | |||
3443 | return (status == ccsr_channel_status_pending_ctx_reload_v() || | ||
3444 | status == ccsr_channel_status_pending_acq_ctx_reload_v() || | ||
3445 | status == ccsr_channel_status_on_pbdma_ctx_reload_v() || | ||
3446 | status == ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() || | ||
3447 | status == ccsr_channel_status_on_eng_ctx_reload_v() || | ||
3448 | status == ccsr_channel_status_on_eng_pending_ctx_reload_v() || | ||
3449 | status == ccsr_channel_status_on_eng_pending_acq_ctx_reload_v()); | ||
3450 | } | ||
3451 | |||
3416 | void gk20a_dump_channel_status_ramfc(struct gk20a *g, | 3452 | void gk20a_dump_channel_status_ramfc(struct gk20a *g, |
3417 | struct gk20a_debug_output *o, | 3453 | struct gk20a_debug_output *o, |
3418 | u32 chid, | 3454 | u32 chid, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index d5b686f0..70c70931 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -248,6 +248,9 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, | |||
248 | bool wait_for_idle); | 248 | bool wait_for_idle); |
249 | int gk20a_fifo_disable_all_engine_activity(struct gk20a *g, | 249 | int gk20a_fifo_disable_all_engine_activity(struct gk20a *g, |
250 | bool wait_for_idle); | 250 | bool wait_for_idle); |
251 | void gk20a_fifo_enable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg); | ||
252 | void gk20a_fifo_disable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg); | ||
253 | |||
251 | u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 chid); | 254 | u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 chid); |
252 | 255 | ||
253 | int gk20a_fifo_reschedule_runlist(struct gk20a *g, u32 runlist_id); | 256 | int gk20a_fifo_reschedule_runlist(struct gk20a *g, u32 runlist_id); |
@@ -362,6 +365,9 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index); | |||
362 | void gk20a_fifo_enable_channel(struct channel_gk20a *ch); | 365 | void gk20a_fifo_enable_channel(struct channel_gk20a *ch); |
363 | void gk20a_fifo_disable_channel(struct channel_gk20a *ch); | 366 | void gk20a_fifo_disable_channel(struct channel_gk20a *ch); |
364 | 367 | ||
368 | bool gk20a_fifo_channel_status_is_next(struct gk20a *g, u32 chid); | ||
369 | bool gk20a_fifo_channel_status_is_ctx_reload(struct gk20a *g, u32 chid); | ||
370 | |||
365 | struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr); | 371 | struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr); |
366 | void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a); | 372 | void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a); |
367 | 373 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index f3e87a13..eabb98ea 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -29,13 +29,37 @@ int gk20a_enable_tsg(struct tsg_gk20a *tsg) | |||
29 | { | 29 | { |
30 | struct gk20a *g = tsg->g; | 30 | struct gk20a *g = tsg->g; |
31 | struct channel_gk20a *ch; | 31 | struct channel_gk20a *ch; |
32 | bool is_next, is_ctx_reload; | ||
32 | 33 | ||
34 | gk20a_fifo_disable_tsg_sched(g, tsg); | ||
35 | |||
36 | /* | ||
37 | * Due to h/w bug that exists in Maxwell and Pascal, | ||
38 | * we first need to enable all channels with NEXT and CTX_RELOAD set, | ||
39 | * and then rest of the channels should be enabled | ||
40 | */ | ||
33 | down_read(&tsg->ch_list_lock); | 41 | down_read(&tsg->ch_list_lock); |
34 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { | 42 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { |
43 | is_next = gk20a_fifo_channel_status_is_next(g, ch->chid); | ||
44 | is_ctx_reload = gk20a_fifo_channel_status_is_ctx_reload(g, ch->chid); | ||
45 | |||
46 | if (is_next || is_ctx_reload) | ||
47 | g->ops.fifo.enable_channel(ch); | ||
48 | } | ||
49 | |||
50 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { | ||
51 | is_next = gk20a_fifo_channel_status_is_next(g, ch->chid); | ||
52 | is_ctx_reload = gk20a_fifo_channel_status_is_ctx_reload(g, ch->chid); | ||
53 | |||
54 | if (is_next || is_ctx_reload) | ||
55 | continue; | ||
56 | |||
35 | g->ops.fifo.enable_channel(ch); | 57 | g->ops.fifo.enable_channel(ch); |
36 | } | 58 | } |
37 | up_read(&tsg->ch_list_lock); | 59 | up_read(&tsg->ch_list_lock); |
38 | 60 | ||
61 | gk20a_fifo_enable_tsg_sched(g, tsg); | ||
62 | |||
39 | return 0; | 63 | return 0; |
40 | } | 64 | } |
41 | 65 | ||