diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 131 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 343 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.h | 15 |
4 files changed, 72 insertions, 419 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e586913e..8f3900a1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1127,7 +1127,7 @@ struct gk20a { | |||
1127 | struct clk_gk20a clk; | 1127 | struct clk_gk20a clk; |
1128 | struct fifo_gk20a fifo; | 1128 | struct fifo_gk20a fifo; |
1129 | struct gr_gk20a gr; | 1129 | struct gr_gk20a gr; |
1130 | struct sim_gk20a sim; | 1130 | struct sim_gk20a *sim; |
1131 | struct mm_gk20a mm; | 1131 | struct mm_gk20a mm; |
1132 | struct nvgpu_pmu pmu; | 1132 | struct nvgpu_pmu pmu; |
1133 | struct acr_desc acr; | 1133 | struct acr_desc acr; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index d496b7b9..146b0e22 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | |||
@@ -41,47 +41,52 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
41 | g->gr.ctx_vars.dynamic = true; | 41 | g->gr.ctx_vars.dynamic = true; |
42 | g->gr.netlist = GR_NETLIST_DYNAMIC; | 42 | g->gr.netlist = GR_NETLIST_DYNAMIC; |
43 | 43 | ||
44 | if(!g->sim->esc_readl) { | ||
45 | nvgpu_err(g, "Invalid pointer to query function."); | ||
46 | goto fail; | ||
47 | } | ||
48 | |||
44 | /* query sizes and counts */ | 49 | /* query sizes and counts */ |
45 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, | 50 | g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, |
46 | &g->gr.ctx_vars.ucode.fecs.inst.count); | 51 | &g->gr.ctx_vars.ucode.fecs.inst.count); |
47 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, | 52 | g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, |
48 | &g->gr.ctx_vars.ucode.fecs.data.count); | 53 | &g->gr.ctx_vars.ucode.fecs.data.count); |
49 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, | 54 | g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, |
50 | &g->gr.ctx_vars.ucode.gpccs.inst.count); | 55 | &g->gr.ctx_vars.ucode.gpccs.inst.count); |
51 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, | 56 | g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, |
52 | &g->gr.ctx_vars.ucode.gpccs.data.count); | 57 | &g->gr.ctx_vars.ucode.gpccs.data.count); |
53 | gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); | 58 | g->sim->esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); |
54 | g->gr.ctx_vars.buffer_size = temp << 2; | 59 | g->gr.ctx_vars.buffer_size = temp << 2; |
55 | gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, | 60 | g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, |
56 | &g->gr.ctx_vars.sw_bundle_init.count); | 61 | &g->gr.ctx_vars.sw_bundle_init.count); |
57 | gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, | 62 | g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, |
58 | &g->gr.ctx_vars.sw_method_init.count); | 63 | &g->gr.ctx_vars.sw_method_init.count); |
59 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, | 64 | g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, |
60 | &g->gr.ctx_vars.sw_ctx_load.count); | 65 | &g->gr.ctx_vars.sw_ctx_load.count); |
61 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, | 66 | g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, |
62 | &g->gr.ctx_vars.sw_veid_bundle_init.count); | 67 | &g->gr.ctx_vars.sw_veid_bundle_init.count); |
63 | 68 | ||
64 | gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, | 69 | g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, |
65 | &g->gr.ctx_vars.sw_non_ctx_load.count); | 70 | &g->gr.ctx_vars.sw_non_ctx_load.count); |
66 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, | 71 | g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, |
67 | &g->gr.ctx_vars.ctxsw_regs.sys.count); | 72 | &g->gr.ctx_vars.ctxsw_regs.sys.count); |
68 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, | 73 | g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, |
69 | &g->gr.ctx_vars.ctxsw_regs.gpc.count); | 74 | &g->gr.ctx_vars.ctxsw_regs.gpc.count); |
70 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, | 75 | g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, |
71 | &g->gr.ctx_vars.ctxsw_regs.tpc.count); | 76 | &g->gr.ctx_vars.ctxsw_regs.tpc.count); |
72 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, | 77 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, |
73 | &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count); | 78 | &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count); |
74 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, | 79 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, |
75 | &g->gr.ctx_vars.ctxsw_regs.pm_sys.count); | 80 | &g->gr.ctx_vars.ctxsw_regs.pm_sys.count); |
76 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, | 81 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, |
77 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); | 82 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); |
78 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, | 83 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, |
79 | &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); | 84 | &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); |
80 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, | 85 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, |
81 | &g->gr.ctx_vars.ctxsw_regs.ppc.count); | 86 | &g->gr.ctx_vars.ctxsw_regs.ppc.count); |
82 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, | 87 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, |
83 | &g->gr.ctx_vars.ctxsw_regs.etpc.count); | 88 | &g->gr.ctx_vars.ctxsw_regs.etpc.count); |
84 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, | 89 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, |
85 | &g->gr.ctx_vars.ctxsw_regs.ppc.count); | 90 | &g->gr.ctx_vars.ctxsw_regs.ppc.count); |
86 | 91 | ||
87 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); | 92 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); |
@@ -107,152 +112,152 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
107 | goto fail; | 112 | goto fail; |
108 | 113 | ||
109 | for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) | 114 | for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) |
110 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS", | 115 | g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS", |
111 | i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]); | 116 | i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]); |
112 | 117 | ||
113 | for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) | 118 | for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) |
114 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS", | 119 | g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS", |
115 | i, &g->gr.ctx_vars.ucode.fecs.data.l[i]); | 120 | i, &g->gr.ctx_vars.ucode.fecs.data.l[i]); |
116 | 121 | ||
117 | for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) | 122 | for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) |
118 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS", | 123 | g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS", |
119 | i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]); | 124 | i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]); |
120 | 125 | ||
121 | for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) | 126 | for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) |
122 | gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", | 127 | g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", |
123 | i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]); | 128 | i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]); |
124 | 129 | ||
125 | for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) { | 130 | for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) { |
126 | struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l; | 131 | struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l; |
127 | gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", | 132 | g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", |
128 | i, &l[i].addr); | 133 | i, &l[i].addr); |
129 | gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", | 134 | g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", |
130 | i, &l[i].value); | 135 | i, &l[i].value); |
131 | } | 136 | } |
132 | 137 | ||
133 | for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) { | 138 | for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) { |
134 | struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l; | 139 | struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l; |
135 | gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", | 140 | g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", |
136 | i, &l[i].addr); | 141 | i, &l[i].addr); |
137 | gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", | 142 | g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", |
138 | i, &l[i].value); | 143 | i, &l[i].value); |
139 | } | 144 | } |
140 | 145 | ||
141 | for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) { | 146 | for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) { |
142 | struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l; | 147 | struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l; |
143 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", | 148 | g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", |
144 | i, &l[i].addr); | 149 | i, &l[i].addr); |
145 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", | 150 | g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", |
146 | i, &l[i].index); | 151 | i, &l[i].index); |
147 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", | 152 | g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", |
148 | i, &l[i].value); | 153 | i, &l[i].value); |
149 | } | 154 | } |
150 | 155 | ||
151 | for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) { | 156 | for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) { |
152 | struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l; | 157 | struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l; |
153 | gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG", | 158 | g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:REG", |
154 | i, &l[i].addr); | 159 | i, &l[i].addr); |
155 | gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", | 160 | g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", |
156 | i, &l[i].value); | 161 | i, &l[i].value); |
157 | } | 162 | } |
158 | 163 | ||
159 | for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { | 164 | for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { |
160 | struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; | 165 | struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; |
161 | 166 | ||
162 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", | 167 | g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", |
163 | i, &l[i].addr); | 168 | i, &l[i].addr); |
164 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", | 169 | g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", |
165 | i, &l[i].value); | 170 | i, &l[i].value); |
166 | } | 171 | } |
167 | 172 | ||
168 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { | 173 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { |
169 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; | 174 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; |
170 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", | 175 | g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", |
171 | i, &l[i].addr); | 176 | i, &l[i].addr); |
172 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", | 177 | g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", |
173 | i, &l[i].index); | 178 | i, &l[i].index); |
174 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", | 179 | g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", |
175 | i, &l[i].value); | 180 | i, &l[i].value); |
176 | } | 181 | } |
177 | 182 | ||
178 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) { | 183 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) { |
179 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l; | 184 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l; |
180 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", | 185 | g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", |
181 | i, &l[i].addr); | 186 | i, &l[i].addr); |
182 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", | 187 | g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", |
183 | i, &l[i].index); | 188 | i, &l[i].index); |
184 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", | 189 | g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", |
185 | i, &l[i].value); | 190 | i, &l[i].value); |
186 | } | 191 | } |
187 | 192 | ||
188 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) { | 193 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) { |
189 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l; | 194 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l; |
190 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", | 195 | g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", |
191 | i, &l[i].addr); | 196 | i, &l[i].addr); |
192 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", | 197 | g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", |
193 | i, &l[i].index); | 198 | i, &l[i].index); |
194 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", | 199 | g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", |
195 | i, &l[i].value); | 200 | i, &l[i].value); |
196 | } | 201 | } |
197 | 202 | ||
198 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) { | 203 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) { |
199 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l; | 204 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l; |
200 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", | 205 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", |
201 | i, &l[i].addr); | 206 | i, &l[i].addr); |
202 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", | 207 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", |
203 | i, &l[i].index); | 208 | i, &l[i].index); |
204 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", | 209 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", |
205 | i, &l[i].value); | 210 | i, &l[i].value); |
206 | } | 211 | } |
207 | 212 | ||
208 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) { | 213 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) { |
209 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l; | 214 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l; |
210 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", | 215 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", |
211 | i, &l[i].addr); | 216 | i, &l[i].addr); |
212 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", | 217 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", |
213 | i, &l[i].index); | 218 | i, &l[i].index); |
214 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", | 219 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", |
215 | i, &l[i].value); | 220 | i, &l[i].value); |
216 | } | 221 | } |
217 | 222 | ||
218 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) { | 223 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) { |
219 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l; | 224 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l; |
220 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", | 225 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", |
221 | i, &l[i].addr); | 226 | i, &l[i].addr); |
222 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", | 227 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", |
223 | i, &l[i].index); | 228 | i, &l[i].index); |
224 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", | 229 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", |
225 | i, &l[i].value); | 230 | i, &l[i].value); |
226 | } | 231 | } |
227 | 232 | ||
228 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) { | 233 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) { |
229 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l; | 234 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l; |
230 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", | 235 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", |
231 | i, &l[i].addr); | 236 | i, &l[i].addr); |
232 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", | 237 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", |
233 | i, &l[i].index); | 238 | i, &l[i].index); |
234 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", | 239 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", |
235 | i, &l[i].value); | 240 | i, &l[i].value); |
236 | } | 241 | } |
237 | 242 | ||
238 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) { | 243 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) { |
239 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l; | 244 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l; |
240 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", | 245 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", |
241 | i, &l[i].addr); | 246 | i, &l[i].addr); |
242 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", | 247 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", |
243 | i, &l[i].index); | 248 | i, &l[i].index); |
244 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", | 249 | g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", |
245 | i, &l[i].value); | 250 | i, &l[i].value); |
246 | } | 251 | } |
247 | 252 | ||
248 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); | 253 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); |
249 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { | 254 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { |
250 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; | 255 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; |
251 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", | 256 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", |
252 | i, &l[i].addr); | 257 | i, &l[i].addr); |
253 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", | 258 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", |
254 | i, &l[i].index); | 259 | i, &l[i].index); |
255 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", | 260 | g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", |
256 | i, &l[i].value); | 261 | i, &l[i].value); |
257 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, | 262 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, |
258 | "addr:0x%#08x index:0x%08x value:0x%08x", | 263 | "addr:0x%#08x index:0x%08x value:0x%08x", |
@@ -261,7 +266,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
261 | 266 | ||
262 | g->gr.ctx_vars.valid = true; | 267 | g->gr.ctx_vars.valid = true; |
263 | 268 | ||
264 | gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, | 269 | g->sim->esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, |
265 | &g->gr.ctx_vars.regs_base_index); | 270 | &g->gr.ctx_vars.regs_base_index); |
266 | 271 | ||
267 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib"); | 272 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib"); |
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c deleted file mode 100644 index ab064710..00000000 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c +++ /dev/null | |||
@@ -1,343 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <linux/io.h> | ||
24 | #include <linux/highmem.h> | ||
25 | #include <linux/platform_device.h> | ||
26 | |||
27 | #include <nvgpu/log.h> | ||
28 | #include <nvgpu/linux/vm.h> | ||
29 | |||
30 | #include "gk20a.h" | ||
31 | |||
32 | #include <nvgpu/hw/gk20a/hw_sim_gk20a.h> | ||
33 | |||
34 | static inline void sim_writel(struct gk20a *g, u32 r, u32 v) | ||
35 | { | ||
36 | writel(v, g->sim.regs + r); | ||
37 | } | ||
38 | |||
39 | static inline u32 sim_readl(struct gk20a *g, u32 r) | ||
40 | { | ||
41 | return readl(g->sim.regs + r); | ||
42 | } | ||
43 | |||
44 | static void kunmap_and_free_iopage(void **kvaddr, struct page **page) | ||
45 | { | ||
46 | if (*kvaddr) { | ||
47 | kunmap(*kvaddr); | ||
48 | *kvaddr = NULL; | ||
49 | } | ||
50 | if (*page) { | ||
51 | __free_page(*page); | ||
52 | *page = NULL; | ||
53 | } | ||
54 | } | ||
55 | |||
56 | static void gk20a_free_sim_support(struct gk20a *g) | ||
57 | { | ||
58 | /* free sim mappings, bfrs */ | ||
59 | kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, | ||
60 | &g->sim.send_bfr.page); | ||
61 | |||
62 | kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, | ||
63 | &g->sim.recv_bfr.page); | ||
64 | |||
65 | kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, | ||
66 | &g->sim.msg_bfr.page); | ||
67 | } | ||
68 | |||
69 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | ||
70 | { | ||
71 | struct gk20a *g = s->g; | ||
72 | if (g->sim.regs) | ||
73 | sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); | ||
74 | gk20a_free_sim_support(g); | ||
75 | } | ||
76 | |||
77 | static int alloc_and_kmap_iopage(struct gk20a *g, | ||
78 | void **kvaddr, | ||
79 | u64 *phys, | ||
80 | struct page **page) | ||
81 | { | ||
82 | int err = 0; | ||
83 | *page = alloc_page(GFP_KERNEL); | ||
84 | |||
85 | if (!*page) { | ||
86 | err = -ENOMEM; | ||
87 | nvgpu_err(g, "couldn't allocate io page"); | ||
88 | goto fail; | ||
89 | } | ||
90 | |||
91 | *kvaddr = kmap(*page); | ||
92 | if (!*kvaddr) { | ||
93 | err = -ENOMEM; | ||
94 | nvgpu_err(g, "couldn't kmap io page"); | ||
95 | goto fail; | ||
96 | } | ||
97 | *phys = page_to_phys(*page); | ||
98 | return 0; | ||
99 | |||
100 | fail: | ||
101 | kunmap_and_free_iopage(kvaddr, page); | ||
102 | return err; | ||
103 | |||
104 | } | ||
105 | |||
106 | int gk20a_init_sim_support(struct gk20a *g) | ||
107 | { | ||
108 | int err = 0; | ||
109 | u64 phys; | ||
110 | |||
111 | /* allocate sim event/msg buffers */ | ||
112 | err = alloc_and_kmap_iopage(g, &g->sim.send_bfr.kvaddr, | ||
113 | &g->sim.send_bfr.phys, | ||
114 | &g->sim.send_bfr.page); | ||
115 | |||
116 | err = err || alloc_and_kmap_iopage(g, &g->sim.recv_bfr.kvaddr, | ||
117 | &g->sim.recv_bfr.phys, | ||
118 | &g->sim.recv_bfr.page); | ||
119 | |||
120 | err = err || alloc_and_kmap_iopage(g, &g->sim.msg_bfr.kvaddr, | ||
121 | &g->sim.msg_bfr.phys, | ||
122 | &g->sim.msg_bfr.page); | ||
123 | |||
124 | if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && | ||
125 | g->sim.msg_bfr.kvaddr)) { | ||
126 | nvgpu_err(g, "couldn't allocate all sim buffers"); | ||
127 | goto fail; | ||
128 | } | ||
129 | |||
130 | /*mark send ring invalid*/ | ||
131 | sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); | ||
132 | |||
133 | /*read get pointer and make equal to put*/ | ||
134 | g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); | ||
135 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
136 | |||
137 | /*write send ring address and make it valid*/ | ||
138 | phys = g->sim.send_bfr.phys; | ||
139 | sim_writel(g, sim_send_ring_hi_r(), | ||
140 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | ||
141 | sim_writel(g, sim_send_ring_r(), | ||
142 | sim_send_ring_status_valid_f() | | ||
143 | sim_send_ring_target_phys_pci_coherent_f() | | ||
144 | sim_send_ring_size_4kb_f() | | ||
145 | sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
146 | |||
147 | /*repeat for recv ring (but swap put,get as roles are opposite) */ | ||
148 | sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); | ||
149 | |||
150 | /*read put pointer and make equal to get*/ | ||
151 | g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); | ||
152 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
153 | |||
154 | /*write send ring address and make it valid*/ | ||
155 | phys = g->sim.recv_bfr.phys; | ||
156 | sim_writel(g, sim_recv_ring_hi_r(), | ||
157 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | ||
158 | sim_writel(g, sim_recv_ring_r(), | ||
159 | sim_recv_ring_status_valid_f() | | ||
160 | sim_recv_ring_target_phys_pci_coherent_f() | | ||
161 | sim_recv_ring_size_4kb_f() | | ||
162 | sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
163 | |||
164 | g->sim.remove_support = gk20a_remove_sim_support; | ||
165 | return 0; | ||
166 | |||
167 | fail: | ||
168 | gk20a_free_sim_support(g); | ||
169 | return err; | ||
170 | } | ||
171 | |||
172 | static inline u32 sim_msg_header_size(void) | ||
173 | { | ||
174 | return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ | ||
175 | } | ||
176 | |||
177 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | ||
178 | { | ||
179 | return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); | ||
180 | } | ||
181 | |||
182 | static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) | ||
183 | { | ||
184 | return sim_msg_bfr(g, byte_offset); /*starts at 0*/ | ||
185 | } | ||
186 | |||
187 | static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) | ||
188 | { | ||
189 | /*starts after msg header/cmn*/ | ||
190 | return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); | ||
191 | } | ||
192 | |||
193 | static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) | ||
194 | { | ||
195 | /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ | ||
196 | *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); | ||
197 | *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); | ||
198 | *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); | ||
199 | *sim_msg_hdr(g, sim_msg_function_r()) = func; | ||
200 | *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); | ||
201 | } | ||
202 | |||
203 | static inline u32 sim_escape_read_hdr_size(void) | ||
204 | { | ||
205 | return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ | ||
206 | } | ||
207 | |||
208 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
209 | { | ||
210 | return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); | ||
211 | } | ||
212 | |||
213 | static int rpc_send_message(struct gk20a *g) | ||
214 | { | ||
215 | /* calculations done in units of u32s */ | ||
216 | u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; | ||
217 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | ||
218 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | ||
219 | |||
220 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | ||
221 | sim_dma_target_phys_pci_coherent_f() | | ||
222 | sim_dma_status_valid_f() | | ||
223 | sim_dma_size_4kb_f() | | ||
224 | sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); | ||
225 | |||
226 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | ||
227 | u64_hi32(g->sim.msg_bfr.phys); | ||
228 | |||
229 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; | ||
230 | |||
231 | g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % | ||
232 | PAGE_SIZE; | ||
233 | |||
234 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
235 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
236 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
237 | |||
238 | /* Update the put pointer. This will trap into the host. */ | ||
239 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
240 | |||
241 | return 0; | ||
242 | } | ||
243 | |||
244 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
245 | { | ||
246 | return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); | ||
247 | } | ||
248 | |||
249 | static int rpc_recv_poll(struct gk20a *g) | ||
250 | { | ||
251 | u64 recv_phys_addr; | ||
252 | |||
253 | /* XXX This read is not required (?) */ | ||
254 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | ||
255 | |||
256 | /* Poll the recv ring get pointer in an infinite loop*/ | ||
257 | do { | ||
258 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
259 | } while (g->sim.recv_ring_put == g->sim.recv_ring_get); | ||
260 | |||
261 | /* process all replies */ | ||
262 | while (g->sim.recv_ring_put != g->sim.recv_ring_get) { | ||
263 | /* these are in u32 offsets*/ | ||
264 | u32 dma_lo_offset = | ||
265 | sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; | ||
266 | u32 dma_hi_offset = dma_lo_offset + 1; | ||
267 | u32 recv_phys_addr_lo = sim_dma_addr_lo_v( | ||
268 | *sim_recv_ring_bfr(g, dma_lo_offset*4)); | ||
269 | u32 recv_phys_addr_hi = sim_dma_hi_addr_v( | ||
270 | *sim_recv_ring_bfr(g, dma_hi_offset*4)); | ||
271 | |||
272 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | ||
273 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | ||
274 | |||
275 | if (recv_phys_addr != g->sim.msg_bfr.phys) { | ||
276 | nvgpu_err(g, "%s Error in RPC reply", | ||
277 | __func__); | ||
278 | return -1; | ||
279 | } | ||
280 | |||
281 | /* Update GET pointer */ | ||
282 | g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % | ||
283 | PAGE_SIZE; | ||
284 | |||
285 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
286 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
287 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
288 | |||
289 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
290 | |||
291 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
292 | } | ||
293 | |||
294 | return 0; | ||
295 | } | ||
296 | |||
297 | static int issue_rpc_and_wait(struct gk20a *g) | ||
298 | { | ||
299 | int err; | ||
300 | |||
301 | err = rpc_send_message(g); | ||
302 | if (err) { | ||
303 | nvgpu_err(g, "%s failed rpc_send_message", | ||
304 | __func__); | ||
305 | return err; | ||
306 | } | ||
307 | |||
308 | err = rpc_recv_poll(g); | ||
309 | if (err) { | ||
310 | nvgpu_err(g, "%s failed rpc_recv_poll", | ||
311 | __func__); | ||
312 | return err; | ||
313 | } | ||
314 | |||
315 | /* Now check if RPC really succeeded */ | ||
316 | if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { | ||
317 | nvgpu_err(g, "%s received failed status!", | ||
318 | __func__); | ||
319 | return -(*sim_msg_hdr(g, sim_msg_result_r())); | ||
320 | } | ||
321 | return 0; | ||
322 | } | ||
323 | |||
324 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) | ||
325 | { | ||
326 | int err; | ||
327 | size_t pathlen = strlen(path); | ||
328 | u32 data_offset; | ||
329 | |||
330 | sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), | ||
331 | sim_escape_read_hdr_size()); | ||
332 | *sim_msg_param(g, 0) = index; | ||
333 | *sim_msg_param(g, 4) = sizeof(u32); | ||
334 | data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); | ||
335 | *sim_msg_param(g, 8) = data_offset; | ||
336 | strcpy((char *)sim_msg_param(g, 0xc), path); | ||
337 | |||
338 | err = issue_rpc_and_wait(g); | ||
339 | |||
340 | if (!err) | ||
341 | memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); | ||
342 | return err; | ||
343 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h index 44378e7a..8f23abd8 100644 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A sim support | 4 | * GK20A sim support |
5 | * | 5 | * |
6 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), | 9 | * copy of this software and associated documentation files (the "Software"), |
@@ -27,25 +27,16 @@ | |||
27 | #define __SIM_GK20A_H__ | 27 | #define __SIM_GK20A_H__ |
28 | 28 | ||
29 | struct gk20a; | 29 | struct gk20a; |
30 | struct platform_device; | ||
31 | 30 | ||
32 | struct sim_gk20a { | 31 | struct sim_gk20a { |
33 | struct gk20a *g; | 32 | struct gk20a *g; |
34 | struct resource *reg_mem; | ||
35 | void __iomem *regs; | ||
36 | struct { | ||
37 | struct page *page; | ||
38 | void *kvaddr; | ||
39 | u64 phys; | ||
40 | } send_bfr, recv_bfr, msg_bfr; | ||
41 | u32 send_ring_put; | 33 | u32 send_ring_put; |
42 | u32 recv_ring_get; | 34 | u32 recv_ring_get; |
43 | u32 recv_ring_put; | 35 | u32 recv_ring_put; |
44 | u32 sequence_base; | 36 | u32 sequence_base; |
45 | void (*remove_support)(struct sim_gk20a *); | 37 | void (*remove_support)(struct sim_gk20a *); |
38 | int (*esc_readl)( | ||
39 | struct gk20a *g, char *path, u32 index, u32 *data); | ||
46 | }; | 40 | }; |
47 | 41 | ||
48 | int gk20a_init_sim_support(struct gk20a *g); | ||
49 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data); | ||
50 | |||
51 | #endif /*__SIM_GK20A_H__*/ | 42 | #endif /*__SIM_GK20A_H__*/ |