6 files changed, 68 insertions, 24 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index f06bf1c5..9dfe3083 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -696,6 +696,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
         u32 active_engine_id, pbdma_id, engine_id;
         int flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ?
                 NVGPU_DMA_FORCE_CONTIGUOUS : 0;
+        int err = 0;
 
         nvgpu_log_fn(g, " ");
 
@@ -733,7 +734,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
                                 f->num_runlist_entries, runlist_size);
 
                 for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) {
-                        int err = nvgpu_dma_alloc_flags_sys(g, flags,
+                        err = nvgpu_dma_alloc_flags_sys(g, flags,
                                                             runlist_size,
                                                             &runlist->mem[i]);
                         if (err) {
@@ -741,7 +742,13 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
                                 goto clean_up_runlist;
                         }
                 }
-                nvgpu_mutex_init(&runlist->runlist_lock);
+
+                err = nvgpu_mutex_init(&runlist->runlist_lock);
+                if (err != 0) {
+                        nvgpu_err(g,
+                                "Error in runlist_lock mutex initialization");
+                        goto clean_up_runlist;
+                }
 
                 /* None of buffers is pinned if this value doesn't change.
                     Otherwise, one of them (cur_buffer) must have been pinned. */
@@ -773,7 +780,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
 clean_up_runlist:
         gk20a_fifo_delete_runlist(f);
         nvgpu_log_fn(g, "fail");
-        return -ENOMEM;
+        return err;
 }
 
 u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index 2f715ae1..5fa4dd53 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -707,9 +707,10 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
         gk20a_falcon_engine_dependency_ops(flcn);
 }
 
-void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
+int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 {
         struct gk20a *g = flcn->g;
+        int err = 0;
 
         switch (flcn->flcn_id) {
         case FALCON_ID_PMU:
@@ -726,28 +727,35 @@ void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
                 flcn->flcn_base = FALCON_FECS_BASE;
                 flcn->is_falcon_supported = true;
                 flcn->is_interrupt_enabled = false;
-        break;
+                break;
         case FALCON_ID_GPCCS:
                 flcn->flcn_base = FALCON_GPCCS_BASE;
                 flcn->is_falcon_supported = true;
                 flcn->is_interrupt_enabled = false;
-        break;
+                break;
         case FALCON_ID_NVDEC:
                 flcn->flcn_base = FALCON_NVDEC_BASE;
                 flcn->is_falcon_supported = false;
                 flcn->is_interrupt_enabled = false;
-        break;
+                break;
         default:
                 flcn->is_falcon_supported = false;
                 nvgpu_err(g, "Invalid flcn request");
+                err = -ENODEV;
                 break;
         }
 
         if (flcn->is_falcon_supported) {
-                nvgpu_mutex_init(&flcn->copy_lock);
-                gk20a_falcon_ops(flcn);
+                err = nvgpu_mutex_init(&flcn->copy_lock);
+                if (err != 0) {
+                        nvgpu_err(g, "Error in flcn.copy_lock mutex initialization");
+                } else {
+                        gk20a_falcon_ops(flcn);
+                }
         } else {
                 nvgpu_log_info(g, "falcon 0x%x not supported on %s",
                         flcn->flcn_id, g->name);
         }
+
+        return err;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
index 95d46251..7f7ee89e 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,7 @@
 #define __FLCN_GK20A_H__
 
 void gk20a_falcon_ops(struct nvgpu_falcon *flcn);
-void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
+int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
 void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn);
 
 #endif /* __FLCN_GK20A_H__ */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index f5e35927..1c34c152 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -150,7 +150,7 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 
 int gk20a_finalize_poweron(struct gk20a *g)
 {
-        int err;
+        int err = 0;
 #if defined(CONFIG_TEGRA_GK20A_NVHOST)
         u32 nr_pages;
 #endif
@@ -182,9 +182,21 @@ int gk20a_finalize_poweron(struct gk20a *g)
         }
 
         /* init interface layer support for PMU falcon */
-        nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
-        nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
-        nvgpu_flcn_sw_init(g, FALCON_ID_NVDEC);
+        err = nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
+        if (err != 0) {
+                nvgpu_err(g, "failed to sw init FALCON_ID_PMU");
+                goto done;
+        }
+        err = nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
+        if (err != 0) {
+                nvgpu_err(g, "failed to sw init FALCON_ID_SEC2");
+                goto done;
+        }
+        err = nvgpu_flcn_sw_init(g, FALCON_ID_NVDEC);
+        if (err != 0) {
+                nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC");
+                goto done;
+        }
 
         if (g->ops.bios.init) {
                 err = g->ops.bios.init(g);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index be00f708..898dfec8 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1263,7 +1263,7 @@ struct gpu_ops {
                 u32 (*get_link_control_status)(struct gk20a *g);
         } xve;
         struct {
-                void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn);
+                int (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn);
         } falcon;
         struct {
                 void (*enable_priv_ring)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 39d6879b..2969743b 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3983,10 +3983,14 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
 int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
 {
         struct zbc_entry zbc_val;
-        u32 i;
-        int err;
+        u32 i = 0;
+        int err = 0;
 
-        nvgpu_mutex_init(&gr->zbc_lock);
+        err = nvgpu_mutex_init(&gr->zbc_lock);
+        if (err != 0) {
+                nvgpu_err(g, "Error in zbc_lock mutex initialization");
+                return err;
+        }
 
         /* load default color table */
         zbc_val.type = GK20A_ZBC_TYPE_COLOR;
@@ -4749,7 +4753,7 @@ static int gr_gk20a_init_access_map(struct gk20a *g)
 static int gk20a_init_gr_setup_sw(struct gk20a *g)
 {
         struct gr_gk20a *gr = &g->gr;
-        int err;
+        int err = 0;
 
         nvgpu_log_fn(g, " ");
 
@@ -4761,7 +4765,11 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
         gr->g = g;
 
 #if defined(CONFIG_GK20A_CYCLE_STATS)
-        nvgpu_mutex_init(&g->gr.cs_lock);
+        err = nvgpu_mutex_init(&g->gr.cs_lock);
+        if (err != 0) {
+                nvgpu_err(g, "Error in gr.cs_lock mutex initialization");
+                return err;
+        }
 #endif
 
         err = gr_gk20a_init_gr_config(g, gr);
@@ -4802,7 +4810,12 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
         if (g->ops.gr.init_gfxp_wfi_timeout_count)
                 g->ops.gr.init_gfxp_wfi_timeout_count(g);
 
-        nvgpu_mutex_init(&gr->ctx_mutex);
+        err = nvgpu_mutex_init(&gr->ctx_mutex);
+        if (err != 0) {
+                nvgpu_err(g, "Error in gr.ctx_mutex initialization");
+                goto clean_up;
+        }
+
         nvgpu_spinlock_init(&gr->ch_tlb_lock);
 
         gr->remove_support = gk20a_remove_gr_support;
@@ -4869,12 +4882,16 @@ static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g)
 
 int gk20a_init_gr_support(struct gk20a *g)
 {
-        u32 err;
+        int err = 0;
 
         nvgpu_log_fn(g, " ");
 
         /* this is required before gr_gk20a_init_ctx_state */
-        nvgpu_mutex_init(&g->gr.fecs_mutex);
+        err = nvgpu_mutex_init(&g->gr.fecs_mutex);
+        if (err != 0) {
+                nvgpu_err(g, "Error in gr.fecs_mutex initialization");
+                return err;
+        }
 
         err = gr_gk20a_init_ctxsw(g);
         if (err)