diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 |
3 files changed, 58 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8f291f92..e0434360 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -285,12 +285,15 @@ struct gpu_ops { | |||
285 | struct channel_gk20a *ch, | 285 | struct channel_gk20a *ch, |
286 | struct gr_gk20a_isr_data *isr_data); | 286 | struct gr_gk20a_isr_data *isr_data); |
287 | int (*pre_process_sm_exception)(struct gk20a *g, | 287 | int (*pre_process_sm_exception)(struct gk20a *g, |
288 | u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, | 288 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, |
289 | bool sm_debugger_attached, | 289 | bool sm_debugger_attached, |
290 | struct channel_gk20a *fault_ch, | 290 | struct channel_gk20a *fault_ch, |
291 | bool *early_exit, bool *ignore_debugger); | 291 | bool *early_exit, bool *ignore_debugger); |
292 | u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); | 292 | u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); |
293 | int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, | 293 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, |
294 | u32 *esr_sm_sel); | ||
295 | int (*handle_sm_exception)(struct gk20a *g, | ||
296 | u32 gpc, u32 tpc, u32 sm, | ||
294 | bool *post_event, struct channel_gk20a *fault_ch, | 297 | bool *post_event, struct channel_gk20a *fault_ch, |
295 | u32 *hww_global_esr); | 298 | u32 *hww_global_esr); |
296 | int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc, | 299 | int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 2afa79f1..2ee2048c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -820,6 +820,23 @@ clean_up_mem: | |||
820 | return ret; | 820 | return ret; |
821 | } | 821 | } |
822 | 822 | ||
823 | u32 gk20a_gr_gpc_offset(struct gk20a *g, u32 gpc) | ||
824 | { | ||
825 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
826 | u32 gpc_offset = gpc_stride * gpc; | ||
827 | |||
828 | return gpc_offset; | ||
829 | } | ||
830 | |||
831 | u32 gk20a_gr_tpc_offset(struct gk20a *g, u32 tpc) | ||
832 | { | ||
833 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
834 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
835 | u32 tpc_offset = tpc_in_gpc_stride * tpc; | ||
836 | |||
837 | return tpc_offset; | ||
838 | } | ||
839 | |||
823 | static int gr_gk20a_commit_global_cb_manager(struct gk20a *g, | 840 | static int gr_gk20a_commit_global_cb_manager(struct gk20a *g, |
824 | struct channel_gk20a *c, bool patch) | 841 | struct channel_gk20a *c, bool patch) |
825 | { | 842 | { |
@@ -6163,7 +6180,7 @@ fail: | |||
6163 | return err; | 6180 | return err; |
6164 | } | 6181 | } |
6165 | 6182 | ||
6166 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 6183 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
6167 | bool *post_event, struct channel_gk20a *fault_ch, | 6184 | bool *post_event, struct channel_gk20a *fault_ch, |
6168 | u32 *hww_global_esr) | 6185 | u32 *hww_global_esr) |
6169 | { | 6186 | { |
@@ -6206,7 +6223,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
6206 | *hww_global_esr = global_esr; | 6223 | *hww_global_esr = global_esr; |
6207 | 6224 | ||
6208 | if (g->ops.gr.pre_process_sm_exception) { | 6225 | if (g->ops.gr.pre_process_sm_exception) { |
6209 | ret = g->ops.gr.pre_process_sm_exception(g, gpc, tpc, | 6226 | ret = g->ops.gr.pre_process_sm_exception(g, gpc, tpc, sm, |
6210 | global_esr, warp_esr, | 6227 | global_esr, warp_esr, |
6211 | sm_debugger_attached, | 6228 | sm_debugger_attached, |
6212 | fault_ch, | 6229 | fault_ch, |
@@ -6290,6 +6307,12 @@ int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
6290 | return ret; | 6307 | return ret; |
6291 | } | 6308 | } |
6292 | 6309 | ||
6310 | void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | ||
6311 | u32 *esr_sm_sel) | ||
6312 | { | ||
6313 | *esr_sm_sel = 1; | ||
6314 | } | ||
6315 | |||
6293 | static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | 6316 | static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, |
6294 | bool *post_event, struct channel_gk20a *fault_ch, | 6317 | bool *post_event, struct channel_gk20a *fault_ch, |
6295 | u32 *hww_global_esr) | 6318 | u32 *hww_global_esr) |
@@ -6300,17 +6323,33 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
6300 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | 6323 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
6301 | u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() | 6324 | u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() |
6302 | + offset); | 6325 | + offset); |
6326 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | ||
6303 | 6327 | ||
6304 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, ""); | 6328 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, ""); |
6305 | 6329 | ||
6306 | /* check if an sm exeption is pending */ | 6330 | /* check if an sm exeption is pending */ |
6307 | if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) == | 6331 | if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) == |
6308 | gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) { | 6332 | gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) { |
6333 | u32 esr_sm_sel, sm; | ||
6334 | |||
6309 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | 6335 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
6310 | "GPC%d TPC%d: SM exception pending", gpc, tpc); | 6336 | "GPC%d TPC%d: SM exception pending", gpc, tpc); |
6311 | ret = g->ops.gr.handle_sm_exception(g, gpc, tpc, | 6337 | g->ops.gr.get_esr_sm_sel(g, gpc, tpc, &esr_sm_sel); |
6312 | post_event, fault_ch, | 6338 | |
6313 | hww_global_esr); | 6339 | for (sm = 0; sm < sm_per_tpc; sm++) { |
6340 | |||
6341 | if (!(esr_sm_sel & (1 << sm))) | ||
6342 | continue; | ||
6343 | |||
6344 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
6345 | "GPC%d TPC%d: SM%d exception pending", | ||
6346 | gpc, tpc, sm); | ||
6347 | |||
6348 | ret = g->ops.gr.handle_sm_exception(g, | ||
6349 | gpc, tpc, sm, post_event, fault_ch, | ||
6350 | hww_global_esr); | ||
6351 | } | ||
6352 | |||
6314 | } | 6353 | } |
6315 | 6354 | ||
6316 | /* check if a tex exeption is pending */ | 6355 | /* check if a tex exeption is pending */ |
@@ -9621,4 +9660,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
9621 | gops->gr.resume_from_pause = gr_gk20a_resume_from_pause; | 9660 | gops->gr.resume_from_pause = gr_gk20a_resume_from_pause; |
9622 | gops->gr.clear_sm_errors = gr_gk20a_clear_sm_errors; | 9661 | gops->gr.clear_sm_errors = gr_gk20a_clear_sm_errors; |
9623 | gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions; | 9662 | gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions; |
9663 | gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel; | ||
9624 | } | 9664 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index de80c5e3..745848ab 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -636,7 +636,7 @@ int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | |||
636 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); | 636 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); |
637 | int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, | 637 | int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, |
638 | u32 expect_delay); | 638 | u32 expect_delay); |
639 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 639 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
640 | bool *post_event, struct channel_gk20a *fault_ch, | 640 | bool *post_event, struct channel_gk20a *fault_ch, |
641 | u32 *hww_global_esr); | 641 | u32 *hww_global_esr); |
642 | int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | 642 | int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, |
@@ -730,6 +730,10 @@ void gr_gk20a_write_zcull_ptr(struct gk20a *g, | |||
730 | void gr_gk20a_write_pm_ptr(struct gk20a *g, | 730 | void gr_gk20a_write_pm_ptr(struct gk20a *g, |
731 | struct nvgpu_mem *mem, u64 gpu_va); | 731 | struct nvgpu_mem *mem, u64 gpu_va); |
732 | 732 | ||
733 | u32 gk20a_gr_gpc_offset(struct gk20a *g, u32 gpc); | ||
734 | u32 gk20a_gr_tpc_offset(struct gk20a *g, u32 tpc); | ||
735 | void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | ||
736 | u32 *esr_sm_sel); | ||
733 | 737 | ||
734 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) | 738 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |
735 | { | 739 | { |