diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 24bb8eda..38d4b555 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -419,22 +419,30 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
419 | static int initialized; | 419 | static int initialized; |
420 | struct clk *ref; | 420 | struct clk *ref; |
421 | unsigned long ref_rate; | 421 | unsigned long ref_rate; |
422 | int err; | ||
422 | 423 | ||
423 | gk20a_dbg_fn(""); | 424 | gk20a_dbg_fn(""); |
424 | 425 | ||
426 | err = nvgpu_mutex_init(&clk->clk_mutex); | ||
427 | if (err) | ||
428 | return err; | ||
429 | |||
425 | if (clk->sw_ready) { | 430 | if (clk->sw_ready) { |
426 | gk20a_dbg_fn("skip init"); | 431 | gk20a_dbg_fn("skip init"); |
427 | return 0; | 432 | return 0; |
428 | } | 433 | } |
429 | 434 | ||
430 | if (!gk20a_clk_get(g)) | 435 | if (!gk20a_clk_get(g)) { |
431 | return -EINVAL; | 436 | err = -EINVAL; |
437 | goto fail; | ||
438 | } | ||
432 | 439 | ||
433 | ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); | 440 | ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); |
434 | if (IS_ERR(ref)) { | 441 | if (IS_ERR(ref)) { |
435 | gk20a_err(dev_from_gk20a(g), | 442 | gk20a_err(dev_from_gk20a(g), |
436 | "failed to get GPCPLL reference clock"); | 443 | "failed to get GPCPLL reference clock"); |
437 | return -EINVAL; | 444 | err = -EINVAL; |
445 | goto fail; | ||
438 | } | 446 | } |
439 | ref_rate = clk_get_rate(ref); | 447 | ref_rate = clk_get_rate(ref); |
440 | 448 | ||
@@ -443,7 +451,8 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
443 | if (clk->gpc_pll.clk_in == 0) { | 451 | if (clk->gpc_pll.clk_in == 0) { |
444 | gk20a_err(dev_from_gk20a(g), | 452 | gk20a_err(dev_from_gk20a(g), |
445 | "GPCPLL reference clock is zero"); | 453 | "GPCPLL reference clock is zero"); |
446 | return -EINVAL; | 454 | err = -EINVAL; |
455 | goto fail; | ||
447 | } | 456 | } |
448 | 457 | ||
449 | /* Decide initial frequency */ | 458 | /* Decide initial frequency */ |
@@ -457,12 +466,14 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
457 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; | 466 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; |
458 | } | 467 | } |
459 | 468 | ||
460 | nvgpu_mutex_init(&clk->clk_mutex); | ||
461 | |||
462 | clk->sw_ready = true; | 469 | clk->sw_ready = true; |
463 | 470 | ||
464 | gk20a_dbg_fn("done"); | 471 | gk20a_dbg_fn("done"); |
465 | return 0; | 472 | return 0; |
473 | |||
474 | fail: | ||
475 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
476 | return err; | ||
466 | } | 477 | } |
467 | 478 | ||
468 | static int gk20a_init_clk_setup_hw(struct gk20a *g) | 479 | static int gk20a_init_clk_setup_hw(struct gk20a *g) |
@@ -684,6 +695,9 @@ static int gk20a_suspend_clk_support(struct gk20a *g) | |||
684 | ret = clk_disable_gpcpll(g, 1); | 695 | ret = clk_disable_gpcpll(g, 1); |
685 | g->clk.clk_hw_on = false; | 696 | g->clk.clk_hw_on = false; |
686 | nvgpu_mutex_release(&g->clk.clk_mutex); | 697 | nvgpu_mutex_release(&g->clk.clk_mutex); |
698 | |||
699 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | ||
700 | |||
687 | return ret; | 701 | return ret; |
688 | } | 702 | } |
689 | 703 | ||