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-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c18
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.h14
4 files changed, 17 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 8d6c3b70..77458917 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -120,7 +120,7 @@ int channel_gk20a_commit_va(struct channel_gk20a *c)
120 nvgpu_log_fn(g, " "); 120 nvgpu_log_fn(g, " ");
121 121
122 g->ops.mm.init_inst_block(&c->inst_block, c->vm, 122 g->ops.mm.init_inst_block(&c->inst_block, c->vm,
123 c->vm->gmmu_page_sizes[gmmu_page_size_big]); 123 c->vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]);
124 124
125 return 0; 125 return 0;
126} 126}
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 262dbb2c..5300f7dd 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -921,7 +921,7 @@ struct gpu_ops {
921 struct nvgpu_sgt *sgt, 921 struct nvgpu_sgt *sgt,
922 u64 buffer_offset, 922 u64 buffer_offset,
923 u64 size, 923 u64 size,
924 int pgsz_idx, 924 u32 pgsz_idx,
925 u8 kind_v, 925 u8 kind_v,
926 u32 ctag_offset, 926 u32 ctag_offset,
927 u32 flags, 927 u32 flags,
@@ -934,7 +934,7 @@ struct gpu_ops {
934 void (*gmmu_unmap)(struct vm_gk20a *vm, 934 void (*gmmu_unmap)(struct vm_gk20a *vm,
935 u64 vaddr, 935 u64 vaddr,
936 u64 size, 936 u64 size,
937 int pgsz_idx, 937 u32 pgsz_idx,
938 bool va_allocated, 938 bool va_allocated,
939 enum gk20a_mem_rw_flag rw_flag, 939 enum gk20a_mem_rw_flag rw_flag,
940 bool sparse, 940 bool sparse,
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index ee63489e..b5626035 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -158,8 +158,8 @@ static void update_gmmu_pde_locked(struct vm_gk20a *vm,
158 u32 pd_offset = pd_offset_from_index(l, pd_idx); 158 u32 pd_offset = pd_offset_from_index(l, pd_idx);
159 u32 pde_v[2] = {0, 0}; 159 u32 pde_v[2] = {0, 0};
160 160
161 small_valid = attrs->pgsz == gmmu_page_size_small; 161 small_valid = attrs->pgsz == GMMU_PAGE_SIZE_SMALL;
162 big_valid = attrs->pgsz == gmmu_page_size_big; 162 big_valid = attrs->pgsz == GMMU_PAGE_SIZE_BIG;
163 163
164 pde_v[0] = gmmu_pde_size_full_f(); 164 pde_v[0] = gmmu_pde_size_full_f();
165 pde_v[0] |= big_valid ? 165 pde_v[0] |= big_valid ?
@@ -283,24 +283,22 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
283 pd_write(g, pd, pd_offset + 1, pte_w[1]); 283 pd_write(g, pd, pd_offset + 1, pte_w[1]);
284} 284}
285 285
286enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g, 286u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
287 const struct gk20a_mmu_level *l, 287 struct nvgpu_gmmu_pd *pd, u32 pd_idx)
288 struct nvgpu_gmmu_pd *pd, u32 pd_idx)
289{ 288{
290 /* 289 /*
291 * big and small page sizes are the same 290 * big and small page sizes are the same
292 */ 291 */
293 return gmmu_page_size_small; 292 return GMMU_PAGE_SIZE_SMALL;
294} 293}
295 294
296enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g, 295u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
297 const struct gk20a_mmu_level *l, 296 struct nvgpu_gmmu_pd *pd, u32 pd_idx)
298 struct nvgpu_gmmu_pd *pd, u32 pd_idx)
299{ 297{
300 /* 298 /*
301 * return invalid 299 * return invalid
302 */ 300 */
303 return gmmu_nr_page_sizes; 301 return GMMU_NR_PAGE_SIZES;
304} 302}
305 303
306const struct gk20a_mmu_level gk20a_mm_levels_64k[] = { 304const struct gk20a_mmu_level gk20a_mm_levels_64k[] = {
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index b99603bb..0827d355 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -139,7 +139,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
139 struct nvgpu_sgt *sgt, 139 struct nvgpu_sgt *sgt,
140 u64 buffer_offset, 140 u64 buffer_offset,
141 u64 size, 141 u64 size,
142 int pgsz_idx, 142 u32 pgsz_idx,
143 u8 kind_v, 143 u8 kind_v,
144 u32 ctag_offset, 144 u32 ctag_offset,
145 u32 flags, 145 u32 flags,
@@ -153,7 +153,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
153void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm, 153void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm,
154 u64 vaddr, 154 u64 vaddr,
155 u64 size, 155 u64 size,
156 int pgsz_idx, 156 u32 pgsz_idx,
157 bool va_allocated, 157 bool va_allocated,
158 enum gk20a_mem_rw_flag rw_flag, 158 enum gk20a_mem_rw_flag rw_flag,
159 bool sparse, 159 bool sparse,
@@ -178,10 +178,8 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,
178extern const struct gk20a_mmu_level gk20a_mm_levels_64k[]; 178extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
179extern const struct gk20a_mmu_level gk20a_mm_levels_128k[]; 179extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
180 180
181enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g, 181u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
182 const struct gk20a_mmu_level *l, 182 struct nvgpu_gmmu_pd *pd, u32 pd_idx);
183 struct nvgpu_gmmu_pd *pd, u32 pd_idx); 183u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
184enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g, 184 struct nvgpu_gmmu_pd *pd, u32 pd_idx);
185 const struct gk20a_mmu_level *l,
186 struct nvgpu_gmmu_pd *pd, u32 pd_idx);
187#endif /* MM_GK20A_H */ 185#endif /* MM_GK20A_H */