diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.h | 3 |
4 files changed, 41 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index ed48253f..c8b094cf 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -93,6 +93,17 @@ int gk20a_detect_chip(struct gk20a *g) | |||
93 | return gpu_init_hal(g); | 93 | return gpu_init_hal(g); |
94 | } | 94 | } |
95 | 95 | ||
96 | static void gk20a_mask_interrupts(struct gk20a *g) | ||
97 | { | ||
98 | if (g->ops.mc.intr_mask != NULL) { | ||
99 | g->ops.mc.intr_mask(g); | ||
100 | } | ||
101 | |||
102 | if (g->ops.mc.log_pending_intrs != NULL) { | ||
103 | g->ops.mc.log_pending_intrs(g); | ||
104 | } | ||
105 | } | ||
106 | |||
96 | int gk20a_prepare_poweroff(struct gk20a *g) | 107 | int gk20a_prepare_poweroff(struct gk20a *g) |
97 | { | 108 | { |
98 | int ret = 0; | 109 | int ret = 0; |
@@ -122,6 +133,8 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
122 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) | 133 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) |
123 | gk20a_deinit_pstate_support(g); | 134 | gk20a_deinit_pstate_support(g); |
124 | 135 | ||
136 | gk20a_mask_interrupts(g); | ||
137 | |||
125 | g->power_on = false; | 138 | g->power_on = false; |
126 | 139 | ||
127 | return ret; | 140 | return ret; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 6d19d8a3..13c8928f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1119,6 +1119,7 @@ struct gpu_ops { | |||
1119 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); | 1119 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); |
1120 | } regops; | 1120 | } regops; |
1121 | struct { | 1121 | struct { |
1122 | void (*intr_mask)(struct gk20a *g); | ||
1122 | void (*intr_enable)(struct gk20a *g); | 1123 | void (*intr_enable)(struct gk20a *g); |
1123 | void (*intr_unit_config)(struct gk20a *g, | 1124 | void (*intr_unit_config)(struct gk20a *g, |
1124 | bool enable, bool is_stalling, u32 unit); | 1125 | bool enable, bool is_stalling, u32 unit); |
@@ -1139,6 +1140,7 @@ struct gpu_ops { | |||
1139 | void (*reset)(struct gk20a *g, u32 units); | 1140 | void (*reset)(struct gk20a *g, u32 units); |
1140 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | 1141 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); |
1141 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); | 1142 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); |
1143 | void (*log_pending_intrs)(struct gk20a *g); | ||
1142 | } mc; | 1144 | } mc; |
1143 | struct { | 1145 | struct { |
1144 | void (*show_dump)(struct gk20a *g, | 1146 | void (*show_dump)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 9ee24ed0..26084bd6 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -121,6 +121,14 @@ u32 mc_gk20a_isr_nonstall(struct gk20a *g) | |||
121 | return ops; | 121 | return ops; |
122 | } | 122 | } |
123 | 123 | ||
124 | void mc_gk20a_intr_mask(struct gk20a *g) | ||
125 | { | ||
126 | nvgpu_writel(g, mc_intr_en_0_r(), | ||
127 | mc_intr_en_0_inta_disabled_f()); | ||
128 | nvgpu_writel(g, mc_intr_en_1_r(), | ||
129 | mc_intr_en_1_inta_disabled_f()); | ||
130 | } | ||
131 | |||
124 | void mc_gk20a_intr_enable(struct gk20a *g) | 132 | void mc_gk20a_intr_enable(struct gk20a *g) |
125 | { | 133 | { |
126 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | 134 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); |
@@ -292,6 +300,21 @@ bool mc_gk20a_is_intr1_pending(struct gk20a *g, | |||
292 | return is_pending; | 300 | return is_pending; |
293 | } | 301 | } |
294 | 302 | ||
303 | void mc_gk20a_log_pending_intrs(struct gk20a *g) | ||
304 | { | ||
305 | u32 intr; | ||
306 | |||
307 | intr = g->ops.mc.intr_stall(g); | ||
308 | if (intr != 0U) { | ||
309 | nvgpu_info(g, "Pending stall intr0=0x%08x", intr); | ||
310 | } | ||
311 | |||
312 | intr = g->ops.mc.intr_nonstall(g); | ||
313 | if (intr != 0U) { | ||
314 | nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); | ||
315 | } | ||
316 | } | ||
317 | |||
295 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) | 318 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) |
296 | { | 319 | { |
297 | bool semaphore_wakeup, post_events; | 320 | bool semaphore_wakeup, post_events; |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h index 1b59d634..0dfdf906 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h | |||
@@ -24,6 +24,7 @@ | |||
24 | #define MC_GK20A_H | 24 | #define MC_GK20A_H |
25 | struct gk20a; | 25 | struct gk20a; |
26 | 26 | ||
27 | void mc_gk20a_intr_mask(struct gk20a *g); | ||
27 | void mc_gk20a_intr_enable(struct gk20a *g); | 28 | void mc_gk20a_intr_enable(struct gk20a *g); |
28 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | 29 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, |
29 | bool is_stalling, u32 mask); | 30 | bool is_stalling, u32 mask); |
@@ -41,5 +42,7 @@ void gk20a_mc_reset(struct gk20a *g, u32 units); | |||
41 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | 42 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); |
42 | bool mc_gk20a_is_intr1_pending(struct gk20a *g, | 43 | bool mc_gk20a_is_intr1_pending(struct gk20a *g, |
43 | enum nvgpu_unit unit, u32 mc_intr_1); | 44 | enum nvgpu_unit unit, u32 mc_intr_1); |
45 | void mc_gk20a_log_pending_intrs(struct gk20a *g); | ||
44 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops); | 46 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops); |
47 | |||
45 | #endif /* MC_GK20A_H */ | 48 | #endif /* MC_GK20A_H */ |