diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 9 |
3 files changed, 24 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 80d85d65..d7fdffb0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -172,6 +172,7 @@ struct gpu_ops { | |||
172 | u32 (*get_num_pce)(struct gk20a *g); | 172 | u32 (*get_num_pce)(struct gk20a *g); |
173 | } ce2; | 173 | } ce2; |
174 | struct { | 174 | struct { |
175 | u32 (*get_patch_slots)(struct gk20a *g); | ||
175 | int (*init_fs_state)(struct gk20a *g); | 176 | int (*init_fs_state)(struct gk20a *g); |
176 | int (*init_preemption_state)(struct gk20a *g); | 177 | int (*init_preemption_state)(struct gk20a *g); |
177 | void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); | 178 | void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 71fe44a3..3c3ddc80 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -714,7 +714,8 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, | |||
714 | if (patch) { | 714 | if (patch) { |
715 | u32 patch_slot = ch_ctx->patch_ctx.data_count * | 715 | u32 patch_slot = ch_ctx->patch_ctx.data_count * |
716 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; | 716 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; |
717 | if (patch_slot > (PATCH_CTX_SLOTS_MAX - | 717 | if (patch_slot > (PATCH_CTX_ENTRIES_FROM_SIZE( |
718 | ch_ctx->patch_ctx.mem.size) - | ||
718 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY)) { | 719 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY)) { |
719 | nvgpu_err(g, "failed to access patch_slot %d", | 720 | nvgpu_err(g, "failed to access patch_slot %d", |
720 | patch_slot); | 721 | patch_slot); |
@@ -2813,17 +2814,29 @@ static void gr_gk20a_free_channel_gr_ctx(struct channel_gk20a *c) | |||
2813 | c->ch_ctx.gr_ctx = NULL; | 2814 | c->ch_ctx.gr_ctx = NULL; |
2814 | } | 2815 | } |
2815 | 2816 | ||
2817 | u32 gr_gk20a_get_patch_slots(struct gk20a *g) | ||
2818 | { | ||
2819 | return PATCH_CTX_SLOTS_PER_PAGE; | ||
2820 | } | ||
2821 | |||
2816 | static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g, | 2822 | static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g, |
2817 | struct channel_gk20a *c) | 2823 | struct channel_gk20a *c) |
2818 | { | 2824 | { |
2819 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; | 2825 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; |
2820 | struct vm_gk20a *ch_vm = c->vm; | 2826 | struct vm_gk20a *ch_vm = c->vm; |
2827 | u32 alloc_size; | ||
2821 | int err = 0; | 2828 | int err = 0; |
2822 | 2829 | ||
2823 | gk20a_dbg_fn(""); | 2830 | gk20a_dbg_fn(""); |
2824 | 2831 | ||
2832 | alloc_size = g->ops.gr.get_patch_slots(g) * | ||
2833 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; | ||
2834 | |||
2835 | nvgpu_log(g, gpu_dbg_info, "patch buffer size in entries: %d", | ||
2836 | alloc_size); | ||
2837 | |||
2825 | err = nvgpu_dma_alloc_map_flags_sys(ch_vm, NVGPU_DMA_NO_KERNEL_MAPPING, | 2838 | err = nvgpu_dma_alloc_map_flags_sys(ch_vm, NVGPU_DMA_NO_KERNEL_MAPPING, |
2826 | PATCH_CTX_SLOTS_MAX * sizeof(u32), &patch_ctx->mem); | 2839 | alloc_size * sizeof(u32), &patch_ctx->mem); |
2827 | if (err) | 2840 | if (err) |
2828 | return err; | 2841 | return err; |
2829 | 2842 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 0a685d01..db1a9514 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -52,8 +52,14 @@ | |||
52 | 52 | ||
53 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ | 53 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ |
54 | 54 | ||
55 | #define PATCH_CTX_SLOTS_MAX 128 | 55 | /* |
56 | * allocate a minimum of 1 page (4KB) worth of patch space, this is 512 entries | ||
57 | * of address and data pairs | ||
58 | */ | ||
56 | #define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2 | 59 | #define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2 |
60 | #define PATCH_CTX_SLOTS_PER_PAGE \ | ||
61 | (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) | ||
62 | #define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) | ||
57 | 63 | ||
58 | struct channel_gk20a; | 64 | struct channel_gk20a; |
59 | struct nvgpu_warpstate; | 65 | struct nvgpu_warpstate; |
@@ -756,5 +762,6 @@ void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | |||
756 | u32 **ovr_perf_regs); | 762 | u32 **ovr_perf_regs); |
757 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, | 763 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, |
758 | struct nvgpu_mem *mem); | 764 | struct nvgpu_mem *mem); |
765 | u32 gr_gk20a_get_patch_slots(struct gk20a *g); | ||
759 | 766 | ||
760 | #endif /*__GR_GK20A_H__*/ | 767 | #endif /*__GR_GK20A_H__*/ |