diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c | 3 |
4 files changed, 40 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c index 45b25425..751c6a19 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2015, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2012-2017, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -26,6 +26,7 @@ | |||
26 | #define __gk20a_gating_reglist_h__ | 26 | #define __gk20a_gating_reglist_h__ |
27 | 27 | ||
28 | #include "gk20a_gating_reglist.h" | 28 | #include "gk20a_gating_reglist.h" |
29 | #include <nvgpu/enabled.h> | ||
29 | 30 | ||
30 | struct gating_desc { | 31 | struct gating_desc { |
31 | u32 addr; | 32 | u32 addr; |
@@ -305,6 +306,10 @@ void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g, | |||
305 | { | 306 | { |
306 | u32 i; | 307 | u32 i; |
307 | u32 size = sizeof(gk20a_slcg_gr) / sizeof(struct gating_desc); | 308 | u32 size = sizeof(gk20a_slcg_gr) / sizeof(struct gating_desc); |
309 | |||
310 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
311 | return; | ||
312 | |||
308 | for (i = 0; i < size; i++) { | 313 | for (i = 0; i < size; i++) { |
309 | if (prod) | 314 | if (prod) |
310 | gk20a_writel(g, gk20a_slcg_gr[i].addr, | 315 | gk20a_writel(g, gk20a_slcg_gr[i].addr, |
@@ -325,6 +330,10 @@ void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, | |||
325 | { | 330 | { |
326 | u32 i; | 331 | u32 i; |
327 | u32 size = sizeof(gk20a_slcg_perf) / sizeof(struct gating_desc); | 332 | u32 size = sizeof(gk20a_slcg_perf) / sizeof(struct gating_desc); |
333 | |||
334 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
335 | return; | ||
336 | |||
328 | for (i = 0; i < size; i++) { | 337 | for (i = 0; i < size; i++) { |
329 | if (prod) | 338 | if (prod) |
330 | gk20a_writel(g, gk20a_slcg_perf[i].addr, | 339 | gk20a_writel(g, gk20a_slcg_perf[i].addr, |
@@ -340,6 +349,10 @@ void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g, | |||
340 | { | 349 | { |
341 | u32 i; | 350 | u32 i; |
342 | u32 size = sizeof(gk20a_blcg_gr) / sizeof(struct gating_desc); | 351 | u32 size = sizeof(gk20a_blcg_gr) / sizeof(struct gating_desc); |
352 | |||
353 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
354 | return; | ||
355 | |||
343 | for (i = 0; i < size; i++) { | 356 | for (i = 0; i < size; i++) { |
344 | if (prod) | 357 | if (prod) |
345 | gk20a_writel(g, gk20a_blcg_gr[i].addr, | 358 | gk20a_writel(g, gk20a_blcg_gr[i].addr, |
@@ -355,6 +368,10 @@ void gr_gk20a_pg_gr_load_gating_prod(struct gk20a *g, | |||
355 | { | 368 | { |
356 | u32 i; | 369 | u32 i; |
357 | u32 size = sizeof(gk20a_pg_gr) / sizeof(struct gating_desc); | 370 | u32 size = sizeof(gk20a_pg_gr) / sizeof(struct gating_desc); |
371 | |||
372 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
373 | return; | ||
374 | |||
358 | for (i = 0; i < size; i++) { | 375 | for (i = 0; i < size; i++) { |
359 | if (prod) | 376 | if (prod) |
360 | gk20a_writel(g, gk20a_pg_gr[i].addr, | 377 | gk20a_writel(g, gk20a_pg_gr[i].addr, |
@@ -370,6 +387,10 @@ void gr_gk20a_slcg_therm_load_gating_prod(struct gk20a *g, | |||
370 | { | 387 | { |
371 | u32 i; | 388 | u32 i; |
372 | u32 size = sizeof(gk20a_slcg_therm) / sizeof(struct gating_desc); | 389 | u32 size = sizeof(gk20a_slcg_therm) / sizeof(struct gating_desc); |
390 | |||
391 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
392 | return; | ||
393 | |||
373 | for (i = 0; i < size; i++) { | 394 | for (i = 0; i < size; i++) { |
374 | if (prod) | 395 | if (prod) |
375 | gk20a_writel(g, gk20a_slcg_therm[i].addr, | 396 | gk20a_writel(g, gk20a_slcg_therm[i].addr, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 679b8492..628b6823 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4067,6 +4067,9 @@ void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | |||
4067 | { | 4067 | { |
4068 | u32 gate_ctrl; | 4068 | u32 gate_ctrl; |
4069 | 4069 | ||
4070 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
4071 | return; | ||
4072 | |||
4070 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | 4073 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); |
4071 | 4074 | ||
4072 | switch (mode) { | 4075 | switch (mode) { |
@@ -4095,6 +4098,9 @@ void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | |||
4095 | 4098 | ||
4096 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | 4099 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); |
4097 | 4100 | ||
4101 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) | ||
4102 | return; | ||
4103 | |||
4098 | switch (mode) { | 4104 | switch (mode) { |
4099 | case ELCG_RUN: | 4105 | case ELCG_RUN: |
4100 | gate_ctrl = set_field(gate_ctrl, | 4106 | gate_ctrl = set_field(gate_ctrl, |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index 02a5e519..c2c73b9c 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h | |||
@@ -91,6 +91,15 @@ struct gk20a_platform { | |||
91 | /* Engine Level Clock Gating: true = enable flase = disable */ | 91 | /* Engine Level Clock Gating: true = enable flase = disable */ |
92 | bool enable_elcg; | 92 | bool enable_elcg; |
93 | 93 | ||
94 | /* Should be populated at probe. */ | ||
95 | bool can_slcg; | ||
96 | |||
97 | /* Should be populated at probe. */ | ||
98 | bool can_blcg; | ||
99 | |||
100 | /* Should be populated at probe. */ | ||
101 | bool can_elcg; | ||
102 | |||
94 | /* Engine Level Power Gating: true = enable flase = disable */ | 103 | /* Engine Level Power Gating: true = enable flase = disable */ |
95 | bool enable_elpg; | 104 | bool enable_elpg; |
96 | 105 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c index 43abee5d..90a37c47 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c | |||
@@ -57,6 +57,9 @@ struct gk20a_platform vgpu_tegra_platform = { | |||
57 | .enable_elcg = false, | 57 | .enable_elcg = false, |
58 | .enable_elpg = false, | 58 | .enable_elpg = false, |
59 | .enable_aelpg = false, | 59 | .enable_aelpg = false, |
60 | .can_slcg = false, | ||
61 | .can_blcg = false, | ||
62 | .can_elcg = false, | ||
60 | 63 | ||
61 | .ch_wdt_timeout_ms = 5000, | 64 | .ch_wdt_timeout_ms = 5000, |
62 | 65 | ||