diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 91ffbb7e..a40d93fd 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -345,7 +345,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, | |||
345 | do { | 345 | do { |
346 | /* fmodel: host gets fifo_engine_status(gr) from gr | 346 | /* fmodel: host gets fifo_engine_status(gr) from gr |
347 | only when gr_status is read */ | 347 | only when gr_status is read */ |
348 | gk20a_readl(g, gr_status_r()); | 348 | (void) gk20a_readl(g, gr_status_r()); |
349 | 349 | ||
350 | gr_enabled = gk20a_readl(g, mc_enable_r()) & | 350 | gr_enabled = gk20a_readl(g, mc_enable_r()) & |
351 | mc_enable_pgraph_enabled_f(); | 351 | mc_enable_pgraph_enabled_f(); |
@@ -1482,7 +1482,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1482 | gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() | | 1482 | gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() | |
1483 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() | | 1483 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() | |
1484 | gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f()); | 1484 | gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f()); |
1485 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1485 | (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1486 | nvgpu_udelay(10); | 1486 | nvgpu_udelay(10); |
1487 | 1487 | ||
1488 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), | 1488 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), |
@@ -1495,7 +1495,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1495 | gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() | | 1495 | gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() | |
1496 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() | | 1496 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() | |
1497 | gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f()); | 1497 | gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f()); |
1498 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1498 | (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1499 | nvgpu_udelay(10); | 1499 | nvgpu_udelay(10); |
1500 | 1500 | ||
1501 | if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 1501 | if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index f7631a9c..f9996e71 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -172,7 +172,7 @@ void mc_gk20a_intr_stall_pause(struct gk20a *g) | |||
172 | mc_intr_en_0_inta_disabled_f()); | 172 | mc_intr_en_0_inta_disabled_f()); |
173 | 173 | ||
174 | /* flush previous write */ | 174 | /* flush previous write */ |
175 | gk20a_readl(g, mc_intr_en_0_r()); | 175 | (void) gk20a_readl(g, mc_intr_en_0_r()); |
176 | } | 176 | } |
177 | 177 | ||
178 | void mc_gk20a_intr_stall_resume(struct gk20a *g) | 178 | void mc_gk20a_intr_stall_resume(struct gk20a *g) |
@@ -181,7 +181,7 @@ void mc_gk20a_intr_stall_resume(struct gk20a *g) | |||
181 | mc_intr_en_0_inta_hardware_f()); | 181 | mc_intr_en_0_inta_hardware_f()); |
182 | 182 | ||
183 | /* flush previous write */ | 183 | /* flush previous write */ |
184 | gk20a_readl(g, mc_intr_en_0_r()); | 184 | (void) gk20a_readl(g, mc_intr_en_0_r()); |
185 | } | 185 | } |
186 | 186 | ||
187 | void mc_gk20a_intr_nonstall_pause(struct gk20a *g) | 187 | void mc_gk20a_intr_nonstall_pause(struct gk20a *g) |
@@ -190,7 +190,7 @@ void mc_gk20a_intr_nonstall_pause(struct gk20a *g) | |||
190 | mc_intr_en_0_inta_disabled_f()); | 190 | mc_intr_en_0_inta_disabled_f()); |
191 | 191 | ||
192 | /* flush previous write */ | 192 | /* flush previous write */ |
193 | gk20a_readl(g, mc_intr_en_1_r()); | 193 | (void) gk20a_readl(g, mc_intr_en_1_r()); |
194 | } | 194 | } |
195 | 195 | ||
196 | void mc_gk20a_intr_nonstall_resume(struct gk20a *g) | 196 | void mc_gk20a_intr_nonstall_resume(struct gk20a *g) |
@@ -199,7 +199,7 @@ void mc_gk20a_intr_nonstall_resume(struct gk20a *g) | |||
199 | mc_intr_en_0_inta_hardware_f()); | 199 | mc_intr_en_0_inta_hardware_f()); |
200 | 200 | ||
201 | /* flush previous write */ | 201 | /* flush previous write */ |
202 | gk20a_readl(g, mc_intr_en_1_r()); | 202 | (void) gk20a_readl(g, mc_intr_en_1_r()); |
203 | } | 203 | } |
204 | 204 | ||
205 | u32 mc_gk20a_intr_stall(struct gk20a *g) | 205 | u32 mc_gk20a_intr_stall(struct gk20a *g) |