diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 23 |
4 files changed, 65 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 6a9a22b2..f7f39207 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -997,7 +997,7 @@ clean_up: | |||
997 | return err; | 997 | return err; |
998 | } | 998 | } |
999 | 999 | ||
1000 | static void gk20a_fifo_handle_runlist_event(struct gk20a *g) | 1000 | void gk20a_fifo_handle_runlist_event(struct gk20a *g) |
1001 | { | 1001 | { |
1002 | u32 runlist_event = gk20a_readl(g, fifo_intr_runlist_r()); | 1002 | u32 runlist_event = gk20a_readl(g, fifo_intr_runlist_r()); |
1003 | 1003 | ||
@@ -1276,7 +1276,7 @@ bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) | |||
1276 | return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); | 1276 | return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); |
1277 | } | 1277 | } |
1278 | 1278 | ||
1279 | static bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | 1279 | bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, |
1280 | u32 engine_subid, bool fake_fault) | 1280 | u32 engine_subid, bool fake_fault) |
1281 | { | 1281 | { |
1282 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1282 | u32 engine_enum = ENGINE_INVAL_GK20A; |
@@ -1831,9 +1831,9 @@ void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose) | |||
1831 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1831 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1832 | } | 1832 | } |
1833 | 1833 | ||
1834 | void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | 1834 | void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, |
1835 | u32 hw_id, bool id_is_tsg, | 1835 | u32 hw_id, unsigned int id_type, unsigned int rc_type, |
1836 | bool id_is_known, bool verbose) | 1836 | struct mmu_fault_info *mmfault) |
1837 | { | 1837 | { |
1838 | unsigned long engine_id, i; | 1838 | unsigned long engine_id, i; |
1839 | unsigned long _engine_ids = __engine_ids; | 1839 | unsigned long _engine_ids = __engine_ids; |
@@ -1843,12 +1843,8 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | |||
1843 | u32 ref_type; | 1843 | u32 ref_type; |
1844 | u32 ref_id; | 1844 | u32 ref_id; |
1845 | u32 ref_id_is_tsg = false; | 1845 | u32 ref_id_is_tsg = false; |
1846 | 1846 | bool id_is_known = (id_type != ID_TYPE_UNKNOWN) ? true : false; | |
1847 | if (verbose) | 1847 | bool id_is_tsg = (id_type == ID_TYPE_TSG) ? true : false; |
1848 | gk20a_debug_dump(g->dev); | ||
1849 | |||
1850 | if (g->ops.ltc.flush) | ||
1851 | g->ops.ltc.flush(g); | ||
1852 | 1848 | ||
1853 | if (id_is_known) { | 1849 | if (id_is_known) { |
1854 | engine_ids = gk20a_fifo_engines_on_id(g, hw_id, id_is_tsg); | 1850 | engine_ids = gk20a_fifo_engines_on_id(g, hw_id, id_is_tsg); |
@@ -1916,6 +1912,27 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | |||
1916 | } | 1912 | } |
1917 | } | 1913 | } |
1918 | 1914 | ||
1915 | void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | ||
1916 | u32 hw_id, bool id_is_tsg, | ||
1917 | bool id_is_known, bool verbose) | ||
1918 | { | ||
1919 | unsigned int id_type; | ||
1920 | |||
1921 | if (verbose) | ||
1922 | gk20a_debug_dump(g->dev); | ||
1923 | |||
1924 | if (g->ops.ltc.flush) | ||
1925 | g->ops.ltc.flush(g); | ||
1926 | |||
1927 | if (id_is_known) | ||
1928 | id_type = id_is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL; | ||
1929 | else | ||
1930 | id_type = ID_TYPE_UNKNOWN; | ||
1931 | |||
1932 | g->ops.fifo.teardown_ch_tsg(g, __engine_ids, hw_id, id_type, | ||
1933 | RC_TYPE_NORMAL, NULL); | ||
1934 | } | ||
1935 | |||
1919 | /* force reset channel and tsg (if it's part of one) */ | 1936 | /* force reset channel and tsg (if it's part of one) */ |
1920 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | 1937 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, |
1921 | u32 err_code, bool verbose) | 1938 | u32 err_code, bool verbose) |
@@ -4225,4 +4242,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4225 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; | 4242 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; |
4226 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; | 4243 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; |
4227 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; | 4244 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; |
4245 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | ||
4228 | } | 4246 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index a399e95f..6d1b902e 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -40,6 +40,9 @@ | |||
40 | 40 | ||
41 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 | 41 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 |
42 | 42 | ||
43 | #define RC_TYPE_NORMAL 0 | ||
44 | #define RC_TYPE_MMU_FAULT 1 | ||
45 | |||
43 | /* | 46 | /* |
44 | * Number of entries in the kickoff latency buffer, used to calculate | 47 | * Number of entries in the kickoff latency buffer, used to calculate |
45 | * the profiling and histogram. This number is calculated to be statistically | 48 | * the profiling and histogram. This number is calculated to be statistically |
@@ -376,4 +379,11 @@ int gk20a_fifo_setup_userd(struct channel_gk20a *c); | |||
376 | u32 gk20a_fifo_pbdma_acquire_val(u64 timeout); | 379 | u32 gk20a_fifo_pbdma_acquire_val(u64 timeout); |
377 | 380 | ||
378 | 381 | ||
382 | void gk20a_fifo_handle_runlist_event(struct gk20a *g); | ||
383 | bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | ||
384 | u32 engine_subid, bool fake_fault); | ||
385 | |||
386 | void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, | ||
387 | u32 hw_id, unsigned int id_type, unsigned int rc_type, | ||
388 | struct mmu_fault_info *mmfault); | ||
379 | #endif /*__GR_GK20A_H__*/ | 389 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 1158add1..ec27ed77 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -471,6 +471,9 @@ struct gpu_ops { | |||
471 | int (*reset_enable_hw)(struct gk20a *g); | 471 | int (*reset_enable_hw)(struct gk20a *g); |
472 | int (*setup_userd)(struct channel_gk20a *c); | 472 | int (*setup_userd)(struct channel_gk20a *c); |
473 | u32 (*pbdma_acquire_val)(u64 timeout); | 473 | u32 (*pbdma_acquire_val)(u64 timeout); |
474 | void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask, | ||
475 | u32 id, unsigned int id_type, unsigned int rc_type, | ||
476 | struct mmu_fault_info *mmfault); | ||
474 | } fifo; | 477 | } fifo; |
475 | struct pmu_v { | 478 | struct pmu_v { |
476 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 479 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 3bca7aad..795c9259 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -341,6 +341,29 @@ void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate); | |||
341 | void gk20a_mm_cbc_clean(struct gk20a *g); | 341 | void gk20a_mm_cbc_clean(struct gk20a *g); |
342 | void gk20a_mm_l2_invalidate(struct gk20a *g); | 342 | void gk20a_mm_l2_invalidate(struct gk20a *g); |
343 | 343 | ||
344 | struct mmu_fault_info { | ||
345 | u64 inst_ptr; | ||
346 | u32 inst_aperture; | ||
347 | u64 fault_addr; | ||
348 | u32 fault_addr_aperture; | ||
349 | u32 timestamp_lo; | ||
350 | u32 timestamp_hi; | ||
351 | u32 mmu_engine_id; | ||
352 | u32 gpc_id; | ||
353 | u32 client_type; | ||
354 | u32 client_id; | ||
355 | u32 fault_type; | ||
356 | u32 access_type; | ||
357 | u32 protected_mode; | ||
358 | u32 replayable_fault; | ||
359 | u32 replay_fault_en; | ||
360 | u32 valid; | ||
361 | u32 faulted_pbdma; | ||
362 | u32 faulted_engine; | ||
363 | u32 hw_chid; | ||
364 | struct channel_gk20a *refch; | ||
365 | }; | ||
366 | |||
344 | struct mm_gk20a { | 367 | struct mm_gk20a { |
345 | struct gk20a *g; | 368 | struct gk20a *g; |
346 | 369 | ||