4 files changed, 68 insertions, 36 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
index 68fbb738..7a664bf8 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
@@ -372,41 +372,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c,
         if (!acquire)
                 nvgpu_semaphore_prepare(s, c->hw_sema);
 
-        /* semaphore_a */
-        nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004);
-        /* offset_upper */
-        nvgpu_mem_wr32(g, cmd->mem, off++, (va >> 32) & 0xff);
-        /* semaphore_b */
-        nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005);
-        /* offset */
-        nvgpu_mem_wr32(g, cmd->mem, off++, va & 0xffffffff);
-
-        if (acquire) {
-                /* semaphore_c */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
-                /* payload */
-                nvgpu_mem_wr32(g, cmd->mem, off++,
-                               nvgpu_semaphore_get_value(s));
-                /* semaphore_d */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
-                /* operation: acq_geq, switch_en */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12));
-        } else {
-                /* semaphore_c */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
-                /* payload */
-                nvgpu_mem_wr32(g, cmd->mem, off++,
-                               nvgpu_semaphore_get_value(s));
-                /* semaphore_d */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
-                /* operation: release, wfi */
-                nvgpu_mem_wr32(g, cmd->mem, off++,
-                                0x2 | ((wfi ? 0x0 : 0x1) << 20));
-                /* non_stall_int */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
-                /* ignored */
-                nvgpu_mem_wr32(g, cmd->mem, off++, 0);
-        }
+        g->ops.fifo.add_sema_cmd(g, s, va, cmd, off, acquire, wfi);
 
         if (acquire)
                 gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3d"
@@ -495,7 +461,7 @@ static int __gk20a_channel_semaphore_incr(
                 return -ENOMEM;
         }
 
-        incr_cmd_size = 10;
+        incr_cmd_size = c->g->ops.fifo.get_sema_incr_cmd_size();
         err = gk20a_channel_alloc_priv_cmdbuf(c, incr_cmd_size, incr_cmd);
         if (err) {
                 nvgpu_err(c->g,
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 0c3e8039..aada3065 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -4077,6 +4077,60 @@ const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
         }
 }
 
+u32 gk20a_fifo_get_sema_wait_cmd_size(void)
+{
+        return 8;
+}
+
+u32 gk20a_fifo_get_sema_incr_cmd_size(void)
+{
+        return 10;
+}
+
+void gk20a_fifo_add_sema_cmd(struct gk20a *g,
+        struct nvgpu_semaphore *s, u64 sema_va,
+        struct priv_cmd_entry *cmd,
+        u32 off, bool acquire, bool wfi)
+{
+        nvgpu_log_fn(g, " ");
+
+        /* semaphore_a */
+        nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004);
+        /* offset_upper */
+        nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32) & 0xff);
+        /* semaphore_b */
+        nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005);
+        /* offset */
+        nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffff);
+
+        if (acquire) {
+                /* semaphore_c */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
+                /* payload */
+                nvgpu_mem_wr32(g, cmd->mem, off++,
+                               nvgpu_semaphore_get_value(s));
+                /* semaphore_d */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
+                /* operation: acq_geq, switch_en */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12));
+        } else {
+                /* semaphore_c */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
+                /* payload */
+                nvgpu_mem_wr32(g, cmd->mem, off++,
+                               nvgpu_semaphore_get_value(s));
+                /* semaphore_d */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
+                /* operation: release, wfi */
+                nvgpu_mem_wr32(g, cmd->mem, off++,
+                                0x2 | ((wfi ? 0x0 : 0x1) << 20));
+                /* non_stall_int */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
+                /* ignored */
+                nvgpu_mem_wr32(g, cmd->mem, off++, 0);
+        }
+}
+
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
                 struct priv_cmd_entry *cmd, u32 off,
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 20533f5d..7216302c 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -444,4 +444,10 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
 void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault);
 void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault);
 void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
+u32 gk20a_fifo_get_sema_wait_cmd_size(void);
+u32 gk20a_fifo_get_sema_incr_cmd_size(void);
+void gk20a_fifo_add_sema_cmd(struct gk20a *g,
+        struct nvgpu_semaphore *s, u64 sema_va,
+        struct priv_cmd_entry *cmd,
+        u32 off, bool acquire, bool wfi);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 23e85ee9..17f662df 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -678,6 +678,12 @@ struct gpu_ops {
                         u32 count, u32 buffer_index);
                 int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
                 void (*ring_channel_doorbell)(struct channel_gk20a *c);
+                u32 (*get_sema_wait_cmd_size)(void);
+                u32 (*get_sema_incr_cmd_size)(void);
+                void (*add_sema_cmd)(struct gk20a *g,
+                        struct nvgpu_semaphore *s, u64 sema_va,
+                        struct priv_cmd_entry *cmd,
+                        u32 off, bool acquire, bool wfi);
         } fifo;
         struct pmu_v {
                 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);