diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/tsg_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 885ce172..43ee8d7c 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -367,6 +367,7 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
367 | if(tsg->sm_error_states != NULL) { | 367 | if(tsg->sm_error_states != NULL) { |
368 | nvgpu_kfree(g, tsg->sm_error_states); | 368 | nvgpu_kfree(g, tsg->sm_error_states); |
369 | tsg->sm_error_states = NULL; | 369 | tsg->sm_error_states = NULL; |
370 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
370 | } | 371 | } |
371 | 372 | ||
372 | /* unhook all events created on this TSG */ | 373 | /* unhook all events created on this TSG */ |
@@ -407,6 +408,11 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
407 | int err = 0; | 408 | int err = 0; |
408 | 409 | ||
409 | if (tsg->sm_error_states != NULL) { | 410 | if (tsg->sm_error_states != NULL) { |
411 | return -EINVAL; | ||
412 | } | ||
413 | |||
414 | err = nvgpu_mutex_init(&tsg->sm_exception_mask_lock); | ||
415 | if (err) { | ||
410 | return err; | 416 | return err; |
411 | } | 417 | } |
412 | 418 | ||
@@ -415,6 +421,7 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
415 | * num_sm); | 421 | * num_sm); |
416 | if (tsg->sm_error_states == NULL) { | 422 | if (tsg->sm_error_states == NULL) { |
417 | nvgpu_err(g, "sm_error_states mem allocation failed"); | 423 | nvgpu_err(g, "sm_error_states mem allocation failed"); |
424 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
418 | err = -ENOMEM; | 425 | err = -ENOMEM; |
419 | } | 426 | } |
420 | 427 | ||
@@ -440,3 +447,20 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
440 | tsg_sm_error_states->hww_warp_esr_report_mask = | 447 | tsg_sm_error_states->hww_warp_esr_report_mask = |
441 | sm_error_state->hww_warp_esr_report_mask; | 448 | sm_error_state->hww_warp_esr_report_mask; |
442 | } | 449 | } |
450 | |||
451 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
452 | u32 exception_mask) | ||
453 | { | ||
454 | struct tsg_gk20a *tsg; | ||
455 | |||
456 | tsg = tsg_gk20a_from_ch(ch); | ||
457 | if (!tsg) { | ||
458 | return -EINVAL; | ||
459 | } | ||
460 | |||
461 | nvgpu_mutex_acquire(&tsg->sm_exception_mask_lock); | ||
462 | tsg->sm_exception_mask_type = exception_mask; | ||
463 | nvgpu_mutex_release(&tsg->sm_exception_mask_lock); | ||
464 | |||
465 | return 0; | ||
466 | } | ||