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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/therm_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/therm_gk20a.c109
1 files changed, 109 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
new file mode 100644
index 00000000..de5d0f78
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
@@ -0,0 +1,109 @@
1/*
2 * GK20A Therm
3 *
4 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/enabled.h>
26
27#include "gk20a.h"
28
29#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
30#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
31
32static int gk20a_init_therm_reset_enable_hw(struct gk20a *g)
33{
34 return 0;
35}
36
37static int gk20a_init_therm_setup_sw(struct gk20a *g)
38{
39 return 0;
40}
41
42int gk20a_init_therm_support(struct gk20a *g)
43{
44 u32 err;
45
46 gk20a_dbg_fn("");
47
48 err = gk20a_init_therm_reset_enable_hw(g);
49 if (err)
50 return err;
51
52 err = gk20a_init_therm_setup_sw(g);
53 if (err)
54 return err;
55
56 if (g->ops.therm.init_therm_setup_hw)
57 err = g->ops.therm.init_therm_setup_hw(g);
58 if (err)
59 return err;
60
61#ifdef CONFIG_DEBUG_FS
62 if (g->ops.therm.therm_debugfs_init)
63 g->ops.therm.therm_debugfs_init(g);
64#endif
65
66 return err;
67}
68
69int gk20a_elcg_init_idle_filters(struct gk20a *g)
70{
71 u32 gate_ctrl, idle_filter;
72 u32 engine_id;
73 u32 active_engine_id = 0;
74 struct fifo_gk20a *f = &g->fifo;
75
76 gk20a_dbg_fn("");
77
78 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
79 active_engine_id = f->active_engines_list[engine_id];
80 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
81
82 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
83 gate_ctrl = set_field(gate_ctrl,
84 therm_gate_ctrl_eng_delay_after_m(),
85 therm_gate_ctrl_eng_delay_after_f(4));
86 }
87
88 /* 2 * (1 << 9) = 1024 clks */
89 gate_ctrl = set_field(gate_ctrl,
90 therm_gate_ctrl_eng_idle_filt_exp_m(),
91 therm_gate_ctrl_eng_idle_filt_exp_f(9));
92 gate_ctrl = set_field(gate_ctrl,
93 therm_gate_ctrl_eng_idle_filt_mant_m(),
94 therm_gate_ctrl_eng_idle_filt_mant_f(2));
95 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
96 }
97
98 /* default fecs_idle_filter to 0 */
99 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
100 idle_filter &= ~therm_fecs_idle_filter_value_m();
101 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
102 /* default hubmmu_idle_filter to 0 */
103 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
104 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
105 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
106
107 gk20a_dbg_fn("done");
108 return 0;
109}