diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/sim_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 343 |
1 files changed, 343 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c new file mode 100644 index 00000000..ab064710 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c | |||
@@ -0,0 +1,343 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <linux/io.h> | ||
24 | #include <linux/highmem.h> | ||
25 | #include <linux/platform_device.h> | ||
26 | |||
27 | #include <nvgpu/log.h> | ||
28 | #include <nvgpu/linux/vm.h> | ||
29 | |||
30 | #include "gk20a.h" | ||
31 | |||
32 | #include <nvgpu/hw/gk20a/hw_sim_gk20a.h> | ||
33 | |||
34 | static inline void sim_writel(struct gk20a *g, u32 r, u32 v) | ||
35 | { | ||
36 | writel(v, g->sim.regs + r); | ||
37 | } | ||
38 | |||
39 | static inline u32 sim_readl(struct gk20a *g, u32 r) | ||
40 | { | ||
41 | return readl(g->sim.regs + r); | ||
42 | } | ||
43 | |||
44 | static void kunmap_and_free_iopage(void **kvaddr, struct page **page) | ||
45 | { | ||
46 | if (*kvaddr) { | ||
47 | kunmap(*kvaddr); | ||
48 | *kvaddr = NULL; | ||
49 | } | ||
50 | if (*page) { | ||
51 | __free_page(*page); | ||
52 | *page = NULL; | ||
53 | } | ||
54 | } | ||
55 | |||
56 | static void gk20a_free_sim_support(struct gk20a *g) | ||
57 | { | ||
58 | /* free sim mappings, bfrs */ | ||
59 | kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, | ||
60 | &g->sim.send_bfr.page); | ||
61 | |||
62 | kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, | ||
63 | &g->sim.recv_bfr.page); | ||
64 | |||
65 | kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, | ||
66 | &g->sim.msg_bfr.page); | ||
67 | } | ||
68 | |||
69 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | ||
70 | { | ||
71 | struct gk20a *g = s->g; | ||
72 | if (g->sim.regs) | ||
73 | sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); | ||
74 | gk20a_free_sim_support(g); | ||
75 | } | ||
76 | |||
77 | static int alloc_and_kmap_iopage(struct gk20a *g, | ||
78 | void **kvaddr, | ||
79 | u64 *phys, | ||
80 | struct page **page) | ||
81 | { | ||
82 | int err = 0; | ||
83 | *page = alloc_page(GFP_KERNEL); | ||
84 | |||
85 | if (!*page) { | ||
86 | err = -ENOMEM; | ||
87 | nvgpu_err(g, "couldn't allocate io page"); | ||
88 | goto fail; | ||
89 | } | ||
90 | |||
91 | *kvaddr = kmap(*page); | ||
92 | if (!*kvaddr) { | ||
93 | err = -ENOMEM; | ||
94 | nvgpu_err(g, "couldn't kmap io page"); | ||
95 | goto fail; | ||
96 | } | ||
97 | *phys = page_to_phys(*page); | ||
98 | return 0; | ||
99 | |||
100 | fail: | ||
101 | kunmap_and_free_iopage(kvaddr, page); | ||
102 | return err; | ||
103 | |||
104 | } | ||
105 | |||
106 | int gk20a_init_sim_support(struct gk20a *g) | ||
107 | { | ||
108 | int err = 0; | ||
109 | u64 phys; | ||
110 | |||
111 | /* allocate sim event/msg buffers */ | ||
112 | err = alloc_and_kmap_iopage(g, &g->sim.send_bfr.kvaddr, | ||
113 | &g->sim.send_bfr.phys, | ||
114 | &g->sim.send_bfr.page); | ||
115 | |||
116 | err = err || alloc_and_kmap_iopage(g, &g->sim.recv_bfr.kvaddr, | ||
117 | &g->sim.recv_bfr.phys, | ||
118 | &g->sim.recv_bfr.page); | ||
119 | |||
120 | err = err || alloc_and_kmap_iopage(g, &g->sim.msg_bfr.kvaddr, | ||
121 | &g->sim.msg_bfr.phys, | ||
122 | &g->sim.msg_bfr.page); | ||
123 | |||
124 | if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && | ||
125 | g->sim.msg_bfr.kvaddr)) { | ||
126 | nvgpu_err(g, "couldn't allocate all sim buffers"); | ||
127 | goto fail; | ||
128 | } | ||
129 | |||
130 | /*mark send ring invalid*/ | ||
131 | sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); | ||
132 | |||
133 | /*read get pointer and make equal to put*/ | ||
134 | g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); | ||
135 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
136 | |||
137 | /*write send ring address and make it valid*/ | ||
138 | phys = g->sim.send_bfr.phys; | ||
139 | sim_writel(g, sim_send_ring_hi_r(), | ||
140 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | ||
141 | sim_writel(g, sim_send_ring_r(), | ||
142 | sim_send_ring_status_valid_f() | | ||
143 | sim_send_ring_target_phys_pci_coherent_f() | | ||
144 | sim_send_ring_size_4kb_f() | | ||
145 | sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
146 | |||
147 | /*repeat for recv ring (but swap put,get as roles are opposite) */ | ||
148 | sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); | ||
149 | |||
150 | /*read put pointer and make equal to get*/ | ||
151 | g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); | ||
152 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
153 | |||
154 | /*write send ring address and make it valid*/ | ||
155 | phys = g->sim.recv_bfr.phys; | ||
156 | sim_writel(g, sim_recv_ring_hi_r(), | ||
157 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | ||
158 | sim_writel(g, sim_recv_ring_r(), | ||
159 | sim_recv_ring_status_valid_f() | | ||
160 | sim_recv_ring_target_phys_pci_coherent_f() | | ||
161 | sim_recv_ring_size_4kb_f() | | ||
162 | sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
163 | |||
164 | g->sim.remove_support = gk20a_remove_sim_support; | ||
165 | return 0; | ||
166 | |||
167 | fail: | ||
168 | gk20a_free_sim_support(g); | ||
169 | return err; | ||
170 | } | ||
171 | |||
172 | static inline u32 sim_msg_header_size(void) | ||
173 | { | ||
174 | return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ | ||
175 | } | ||
176 | |||
177 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | ||
178 | { | ||
179 | return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); | ||
180 | } | ||
181 | |||
182 | static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) | ||
183 | { | ||
184 | return sim_msg_bfr(g, byte_offset); /*starts at 0*/ | ||
185 | } | ||
186 | |||
187 | static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) | ||
188 | { | ||
189 | /*starts after msg header/cmn*/ | ||
190 | return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); | ||
191 | } | ||
192 | |||
193 | static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) | ||
194 | { | ||
195 | /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ | ||
196 | *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); | ||
197 | *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); | ||
198 | *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); | ||
199 | *sim_msg_hdr(g, sim_msg_function_r()) = func; | ||
200 | *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); | ||
201 | } | ||
202 | |||
203 | static inline u32 sim_escape_read_hdr_size(void) | ||
204 | { | ||
205 | return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ | ||
206 | } | ||
207 | |||
208 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
209 | { | ||
210 | return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); | ||
211 | } | ||
212 | |||
213 | static int rpc_send_message(struct gk20a *g) | ||
214 | { | ||
215 | /* calculations done in units of u32s */ | ||
216 | u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; | ||
217 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | ||
218 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | ||
219 | |||
220 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | ||
221 | sim_dma_target_phys_pci_coherent_f() | | ||
222 | sim_dma_status_valid_f() | | ||
223 | sim_dma_size_4kb_f() | | ||
224 | sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); | ||
225 | |||
226 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | ||
227 | u64_hi32(g->sim.msg_bfr.phys); | ||
228 | |||
229 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; | ||
230 | |||
231 | g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % | ||
232 | PAGE_SIZE; | ||
233 | |||
234 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
235 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
236 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
237 | |||
238 | /* Update the put pointer. This will trap into the host. */ | ||
239 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
240 | |||
241 | return 0; | ||
242 | } | ||
243 | |||
244 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
245 | { | ||
246 | return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); | ||
247 | } | ||
248 | |||
249 | static int rpc_recv_poll(struct gk20a *g) | ||
250 | { | ||
251 | u64 recv_phys_addr; | ||
252 | |||
253 | /* XXX This read is not required (?) */ | ||
254 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | ||
255 | |||
256 | /* Poll the recv ring get pointer in an infinite loop*/ | ||
257 | do { | ||
258 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
259 | } while (g->sim.recv_ring_put == g->sim.recv_ring_get); | ||
260 | |||
261 | /* process all replies */ | ||
262 | while (g->sim.recv_ring_put != g->sim.recv_ring_get) { | ||
263 | /* these are in u32 offsets*/ | ||
264 | u32 dma_lo_offset = | ||
265 | sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; | ||
266 | u32 dma_hi_offset = dma_lo_offset + 1; | ||
267 | u32 recv_phys_addr_lo = sim_dma_addr_lo_v( | ||
268 | *sim_recv_ring_bfr(g, dma_lo_offset*4)); | ||
269 | u32 recv_phys_addr_hi = sim_dma_hi_addr_v( | ||
270 | *sim_recv_ring_bfr(g, dma_hi_offset*4)); | ||
271 | |||
272 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | ||
273 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | ||
274 | |||
275 | if (recv_phys_addr != g->sim.msg_bfr.phys) { | ||
276 | nvgpu_err(g, "%s Error in RPC reply", | ||
277 | __func__); | ||
278 | return -1; | ||
279 | } | ||
280 | |||
281 | /* Update GET pointer */ | ||
282 | g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % | ||
283 | PAGE_SIZE; | ||
284 | |||
285 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
286 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
287 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
288 | |||
289 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
290 | |||
291 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
292 | } | ||
293 | |||
294 | return 0; | ||
295 | } | ||
296 | |||
297 | static int issue_rpc_and_wait(struct gk20a *g) | ||
298 | { | ||
299 | int err; | ||
300 | |||
301 | err = rpc_send_message(g); | ||
302 | if (err) { | ||
303 | nvgpu_err(g, "%s failed rpc_send_message", | ||
304 | __func__); | ||
305 | return err; | ||
306 | } | ||
307 | |||
308 | err = rpc_recv_poll(g); | ||
309 | if (err) { | ||
310 | nvgpu_err(g, "%s failed rpc_recv_poll", | ||
311 | __func__); | ||
312 | return err; | ||
313 | } | ||
314 | |||
315 | /* Now check if RPC really succeeded */ | ||
316 | if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { | ||
317 | nvgpu_err(g, "%s received failed status!", | ||
318 | __func__); | ||
319 | return -(*sim_msg_hdr(g, sim_msg_result_r())); | ||
320 | } | ||
321 | return 0; | ||
322 | } | ||
323 | |||
324 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) | ||
325 | { | ||
326 | int err; | ||
327 | size_t pathlen = strlen(path); | ||
328 | u32 data_offset; | ||
329 | |||
330 | sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), | ||
331 | sim_escape_read_hdr_size()); | ||
332 | *sim_msg_param(g, 0) = index; | ||
333 | *sim_msg_param(g, 4) = sizeof(u32); | ||
334 | data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); | ||
335 | *sim_msg_param(g, 8) = data_offset; | ||
336 | strcpy((char *)sim_msg_param(g, 0xc), path); | ||
337 | |||
338 | err = issue_rpc_and_wait(g); | ||
339 | |||
340 | if (!err) | ||
341 | memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); | ||
342 | return err; | ||
343 | } | ||