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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h
index 29a01ab8..d96037ce 100644
--- a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h
@@ -21,6 +21,12 @@
21#include "gk20a.h" 21#include "gk20a.h"
22#include "mm_gk20a.h" 22#include "mm_gk20a.h"
23#include "channel_gk20a.h" 23#include "channel_gk20a.h"
24#include "gk20a_allocator.h"
25
26#define gpu_sema_dbg(fmt, args...) \
27 gk20a_dbg(gpu_dbg_sema, fmt, ##args)
28#define gpu_sema_verbose_dbg(fmt, args...) \
29 gk20a_dbg(gpu_dbg_sema_v, fmt, ##args)
24 30
25/* 31/*
26 * Max number of channels that can be used is 512. This of course needs to be 32 * Max number of channels that can be used is 512. This of course needs to be
@@ -274,6 +280,9 @@ static inline void gk20a_semaphore_release(struct gk20a_semaphore *s)
274 return; 280 return;
275 281
276 writel(val, s->hw_sema->value); 282 writel(val, s->hw_sema->value);
283
284 gpu_sema_verbose_dbg("(c=%d) WRITE %u",
285 s->hw_sema->ch->hw_chid, val);
277} 286}
278 287
279/* 288/*
@@ -291,5 +300,9 @@ static inline void gk20a_semaphore_incr(struct gk20a_semaphore *s)
291 300
292 atomic_set(&s->value, atomic_add_return(1, &s->hw_sema->next_value)); 301 atomic_set(&s->value, atomic_add_return(1, &s->hw_sema->next_value));
293 s->incremented = 1; 302 s->incremented = 1;
303
304 gpu_sema_verbose_dbg("INCR sema for c=%d (%u)",
305 s->hw_sema->ch->hw_chid,
306 gk20a_semaphore_next_value(s));
294} 307}
295#endif 308#endif