diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index ed5327cb..dea42b55 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A priv ring | 2 | * GK20A priv ring |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -66,11 +66,11 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
66 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 66 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
67 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); | 67 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); |
68 | 68 | ||
69 | gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," | 69 | nvgpu_log(g, gpu_dbg_intr, "ringmaster intr status0: 0x%08x," |
70 | "status1: 0x%08x", status0, status1); | 70 | "status1: 0x%08x", status0, status1); |
71 | 71 | ||
72 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 72 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
73 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 73 | nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", |
74 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 74 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |
75 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), | 75 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), |
76 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), | 76 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), |
@@ -79,7 +79,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
79 | 79 | ||
80 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | 80 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { |
81 | if (status1 & BIT(gpc)) { | 81 | if (status1 & BIT(gpc)) { |
82 | gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, | 82 | nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, |
83 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), | 83 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), |
84 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), | 84 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), |
85 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), | 85 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), |