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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h30
1 files changed, 28 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 828058b7..292aabb0 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -51,6 +51,7 @@
51/* Mapping between AP_CTRLs and Idle counters */ 51/* Mapping between AP_CTRLs and Idle counters */
52#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) 52#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
53 53
54#define APP_VERSION_GM20B_2 18694072
54#define APP_VERSION_GM20B_1 18547257 55#define APP_VERSION_GM20B_1 18547257
55#define APP_VERSION_GM20B 17615280 56#define APP_VERSION_GM20B 17615280
56#define APP_VERSION_2 18542378 57#define APP_VERSION_2 18542378
@@ -339,6 +340,17 @@ struct pmu_cmdline_args_v1 {
339 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ 340 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
340}; 341};
341 342
343struct pmu_cmdline_args_v2 {
344 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
345 u32 falc_trace_size; /* falctrace buffer size (bytes) */
346 u32 falc_trace_dma_base; /* 256-byte block address */
347 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
348 u8 secure_mode;
349 u8 raise_priv_sec; /*Raise priv level required for desired
350 registers*/
351 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
352};
353
342#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ 354#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
343#define GK20A_PMU_DMEM_BLKSIZE2 8 355#define GK20A_PMU_DMEM_BLKSIZE2 8
344 356
@@ -641,13 +653,23 @@ struct pmu_pg_cmd {
641#define PMU_PERFMON_PCT_TO_INC 58 653#define PMU_PERFMON_PCT_TO_INC 58
642#define PMU_PERFMON_PCT_TO_DEC 23 654#define PMU_PERFMON_PCT_TO_DEC 23
643 655
644struct pmu_perfmon_counter { 656struct pmu_perfmon_counter_v0 {
657 u8 index;
658 u8 flags;
659 u8 group_id;
660 u8 valid;
661 u16 upper_threshold; /* units of 0.01% */
662 u16 lower_threshold; /* units of 0.01% */
663};
664
665struct pmu_perfmon_counter_v2 {
645 u8 index; 666 u8 index;
646 u8 flags; 667 u8 flags;
647 u8 group_id; 668 u8 group_id;
648 u8 valid; 669 u8 valid;
649 u16 upper_threshold; /* units of 0.01% */ 670 u16 upper_threshold; /* units of 0.01% */
650 u16 lower_threshold; /* units of 0.01% */ 671 u16 lower_threshold; /* units of 0.01% */
672 u32 scale;
651}; 673};
652 674
653#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) 675#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
@@ -1044,7 +1066,10 @@ struct pmu_gk20a {
1044 struct mutex elpg_mutex; /* protect elpg enable/disable */ 1066 struct mutex elpg_mutex; /* protect elpg enable/disable */
1045 int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ 1067 int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
1046 1068
1047 struct pmu_perfmon_counter perfmon_counter; 1069 union {
1070 struct pmu_perfmon_counter_v2 perfmon_counter_v2;
1071 struct pmu_perfmon_counter_v0 perfmon_counter_v0;
1072 };
1048 u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; 1073 u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
1049 1074
1050 bool initialized; 1075 bool initialized;
@@ -1063,6 +1088,7 @@ struct pmu_gk20a {
1063 union { 1088 union {
1064 struct pmu_cmdline_args_v0 args_v0; 1089 struct pmu_cmdline_args_v0 args_v0;
1065 struct pmu_cmdline_args_v1 args_v1; 1090 struct pmu_cmdline_args_v1 args_v1;
1091 struct pmu_cmdline_args_v2 args_v2;
1066 }; 1092 };
1067 unsigned long perfmon_events_cnt; 1093 unsigned long perfmon_events_cnt;
1068 bool perfmon_sampling_enabled; 1094 bool perfmon_sampling_enabled;