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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h55
1 files changed, 30 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index bbfcf4ee..683c1dfc 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -680,6 +680,8 @@ enum {
680 PMU_PG_STAT_CMD_ALLOC_DMEM = 0, 680 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
681}; 681};
682 682
683#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
684
683#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) 685#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
684#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) 686#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
685 687
@@ -1135,31 +1137,31 @@ struct pmu_sequence {
1135}; 1137};
1136 1138
1137struct pmu_pg_stats_v1 { 1139struct pmu_pg_stats_v1 {
1138 /* Number of time PMU successfully engaged sleep state */ 1140 /* Number of time PMU successfully engaged sleep state */
1139 u32 entryCount; 1141 u32 entry_count;
1140 /* Number of time PMU exit sleep state */ 1142 /* Number of time PMU exit sleep state */
1141 u32 exitCount; 1143 u32 exit_count;
1142 /* Number of time PMU aborted in entry sequence */ 1144 /* Number of time PMU aborted in entry sequence */
1143 u32 abortCount; 1145 u32 abort_count;
1144 /* 1146 /*
1145 * Time for which GPU was neither in Sleep state not 1147 * Time for which GPU was neither in Sleep state not
1146 * executing sleep sequence. 1148 * executing sleep sequence.
1147 * */ 1149 * */
1148 u32 poweredUpTimeUs; 1150 u32 poweredup_timeus;
1149 /* Entry and exit latency of current sleep cycle */ 1151 /* Entry and exit latency of current sleep cycle */
1150 u32 entryLatencyUs; 1152 u32 entry_latency_us;
1151 u32 exitLatencyUs; 1153 u32 exitlatencyus;
1152 /* Resident time for current sleep cycle. */ 1154 /* Resident time for current sleep cycle. */
1153 u32 residentTimeUs; 1155 u32 resident_timeus;
1154 /* Rolling average entry and exit latencies */ 1156 /* Rolling average entry and exit latencies */
1155 u32 entryLatencyAvgUs; 1157 u32 entrylatency_avgus;
1156 u32 exitLatencyAvgUs; 1158 u32 exitlatency_avgus;
1157 /* Max entry and exit latencies */ 1159 /* Max entry and exit latencies */
1158 u32 entryLatencyMaxUs; 1160 u32 entrylatency_maxus;
1159 u32 exitLatencyMaxUs; 1161 u32 exitlatency_maxus;
1160 /* Total time spent in sleep and non-sleep state */ 1162 /* Total time spent in sleep and non-sleep state */
1161 u32 totalSleepTimeUs; 1163 u32 total_sleep_timeus;
1162 u32 totalNonSleepTimeUs; 1164 u32 total_nonsleep_timeus;
1163}; 1165};
1164 1166
1165struct pmu_pg_stats { 1167struct pmu_pg_stats {
@@ -1369,4 +1371,7 @@ int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout,
1369 u32 *var, u32 val); 1371 u32 *var, u32 val);
1370void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, 1372void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
1371 void *param, u32 handle, u32 status); 1373 void *param, u32 handle, u32 status);
1374void gk20a_pmu_elpg_statistics(struct gk20a *g,
1375 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt);
1376
1372#endif /*__PMU_GK20A_H__*/ 1377#endif /*__PMU_GK20A_H__*/