diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 54 |
1 files changed, 51 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 6cd173e8..73530b22 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -49,7 +49,7 @@ | |||
49 | /* Mapping between AP_CTRLs and Idle counters */ | 49 | /* Mapping between AP_CTRLs and Idle counters */ |
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
51 | 51 | ||
52 | #define APP_VERSION 19123622 | 52 | #define APP_VERSION_T186_0 19494277 |
53 | #define APP_VERSION_GM20B_4 19008461 | 53 | #define APP_VERSION_GM20B_4 19008461 |
54 | #define APP_VERSION_GM20B_3 18935575 | 54 | #define APP_VERSION_GM20B_3 18935575 |
55 | #define APP_VERSION_GM20B_2 18694072 | 55 | #define APP_VERSION_GM20B_2 18694072 |
@@ -304,6 +304,15 @@ enum { | |||
304 | GK20A_PMU_DMAIDX_END = 7 | 304 | GK20A_PMU_DMAIDX_END = 7 |
305 | }; | 305 | }; |
306 | 306 | ||
307 | struct falc_dma_addr { | ||
308 | u32 dma_base; | ||
309 | /*dma_base1 is 9-bit MSB for FB Base | ||
310 | *address for the transfer in FB after | ||
311 | *address using 49b FB address*/ | ||
312 | u16 dma_base1; | ||
313 | u8 dma_offset; | ||
314 | }; | ||
315 | |||
307 | struct pmu_mem_v0 { | 316 | struct pmu_mem_v0 { |
308 | u32 dma_base; | 317 | u32 dma_base; |
309 | u8 dma_offset; | 318 | u8 dma_offset; |
@@ -317,6 +326,12 @@ struct pmu_mem_v1 { | |||
317 | u16 fb_size; | 326 | u16 fb_size; |
318 | }; | 327 | }; |
319 | 328 | ||
329 | struct pmu_mem_v2 { | ||
330 | struct falc_dma_addr dma_addr; | ||
331 | u8 dma_idx; | ||
332 | u16 fb_size; | ||
333 | }; | ||
334 | |||
320 | struct pmu_dmem { | 335 | struct pmu_dmem { |
321 | u16 size; | 336 | u16 size; |
322 | u32 offset; | 337 | u32 offset; |
@@ -363,6 +378,20 @@ struct pmu_cmdline_args_v3 { | |||
363 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | 378 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ |
364 | }; | 379 | }; |
365 | 380 | ||
381 | struct pmu_cmdline_args_v4 { | ||
382 | u32 reserved; | ||
383 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
384 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
385 | struct falc_dma_addr dma_addr; /* 256-byte block address */ | ||
386 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
387 | u8 secure_mode; | ||
388 | u8 raise_priv_sec; /*Raise priv level required for desired | ||
389 | registers*/ | ||
390 | struct pmu_mem_v2 gc6_ctx; /* dmem offset of gc6 context */ | ||
391 | u8 pad; | ||
392 | }; | ||
393 | |||
394 | |||
366 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ | 395 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ |
367 | #define GK20A_PMU_DMEM_BLKSIZE2 8 | 396 | #define GK20A_PMU_DMEM_BLKSIZE2 8 |
368 | 397 | ||
@@ -474,6 +503,13 @@ struct pmu_allocation_v1 { | |||
474 | } alloc; | 503 | } alloc; |
475 | }; | 504 | }; |
476 | 505 | ||
506 | struct pmu_allocation_v2 { | ||
507 | struct { | ||
508 | struct pmu_dmem dmem; | ||
509 | struct pmu_mem_v2 fb; | ||
510 | } alloc; | ||
511 | }; | ||
512 | |||
477 | enum { | 513 | enum { |
478 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | 514 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, |
479 | }; | 515 | }; |
@@ -623,7 +659,7 @@ struct pmu_pg_cmd_elpg_cmd { | |||
623 | u16 cmd; | 659 | u16 cmd; |
624 | }; | 660 | }; |
625 | 661 | ||
626 | struct pmu_pg_cmd_eng_buf_load { | 662 | struct pmu_pg_cmd_eng_buf_load_v0 { |
627 | u8 cmd_type; | 663 | u8 cmd_type; |
628 | u8 engine_id; | 664 | u8 engine_id; |
629 | u8 buf_idx; | 665 | u8 buf_idx; |
@@ -634,6 +670,16 @@ struct pmu_pg_cmd_eng_buf_load { | |||
634 | u8 dma_idx; | 670 | u8 dma_idx; |
635 | }; | 671 | }; |
636 | 672 | ||
673 | struct pmu_pg_cmd_eng_buf_load_v1 { | ||
674 | u8 cmd_type; | ||
675 | u8 engine_id; | ||
676 | u8 buf_idx; | ||
677 | u8 pad; | ||
678 | u16 buf_size; | ||
679 | struct falc_dma_addr dma_addr; /* 256-byte block address */ | ||
680 | u8 dma_idx; | ||
681 | }; | ||
682 | |||
637 | enum { | 683 | enum { |
638 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | 684 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, |
639 | }; | 685 | }; |
@@ -649,7 +695,8 @@ struct pmu_pg_cmd { | |||
649 | union { | 695 | union { |
650 | u8 cmd_type; | 696 | u8 cmd_type; |
651 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | 697 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; |
652 | struct pmu_pg_cmd_eng_buf_load eng_buf_load; | 698 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; |
699 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | ||
653 | struct pmu_pg_cmd_stat stat; | 700 | struct pmu_pg_cmd_stat stat; |
654 | /* TBD: other pg commands */ | 701 | /* TBD: other pg commands */ |
655 | union pmu_ap_cmd ap_cmd; | 702 | union pmu_ap_cmd ap_cmd; |
@@ -1189,6 +1236,7 @@ struct pmu_gk20a { | |||
1189 | struct pmu_cmdline_args_v1 args_v1; | 1236 | struct pmu_cmdline_args_v1 args_v1; |
1190 | struct pmu_cmdline_args_v2 args_v2; | 1237 | struct pmu_cmdline_args_v2 args_v2; |
1191 | struct pmu_cmdline_args_v3 args_v3; | 1238 | struct pmu_cmdline_args_v3 args_v3; |
1239 | struct pmu_cmdline_args_v4 args_v4; | ||
1192 | }; | 1240 | }; |
1193 | unsigned long perfmon_events_cnt; | 1241 | unsigned long perfmon_events_cnt; |
1194 | bool perfmon_sampling_enabled; | 1242 | bool perfmon_sampling_enabled; |