diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 766 |
1 files changed, 3 insertions, 763 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index bbcccdeb..d8af5d7c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -21,6 +21,9 @@ | |||
21 | #ifndef __PMU_GK20A_H__ | 21 | #ifndef __PMU_GK20A_H__ |
22 | #define __PMU_GK20A_H__ | 22 | #define __PMU_GK20A_H__ |
23 | 23 | ||
24 | #include "pmu_api.h" | ||
25 | #include "pmu_common.h" | ||
26 | |||
24 | /* defined by pmu hw spec */ | 27 | /* defined by pmu hw spec */ |
25 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) | 28 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) |
26 | #define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024) | 29 | #define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024) |
@@ -28,27 +31,6 @@ | |||
28 | 31 | ||
29 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) | 32 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) |
30 | 33 | ||
31 | /* PMU Command/Message Interfaces for Adaptive Power */ | ||
32 | /* Macro to get Histogram index */ | ||
33 | #define PMU_AP_HISTOGRAM(idx) (idx) | ||
34 | #define PMU_AP_HISTOGRAM_CONT (4) | ||
35 | |||
36 | /* Total number of histogram bins */ | ||
37 | #define PMU_AP_CFG_HISTOGRAM_BIN_N (16) | ||
38 | |||
39 | /* Mapping between Idle counters and histograms */ | ||
40 | #define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) | ||
41 | #define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) | ||
42 | #define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) | ||
43 | #define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) | ||
44 | |||
45 | |||
46 | /* Mapping between AP_CTRLs and Histograms */ | ||
47 | #define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) | ||
48 | |||
49 | /* Mapping between AP_CTRLs and Idle counters */ | ||
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | ||
51 | |||
52 | #define APP_VERSION_NC_2 20429989 | 34 | #define APP_VERSION_NC_2 20429989 |
53 | #define APP_VERSION_NC_1 20313802 | 35 | #define APP_VERSION_NC_1 20313802 |
54 | #define APP_VERSION_NC_0 20360931 | 36 | #define APP_VERSION_NC_0 20360931 |
@@ -71,240 +53,6 @@ | |||
71 | #define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 | 53 | #define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 |
72 | #define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD | 54 | #define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD |
73 | 55 | ||
74 | |||
75 | enum pmu_perfmon_cmd_start_fields { | ||
76 | COUNTER_ALLOC | ||
77 | }; | ||
78 | |||
79 | /* Adaptive Power Controls (AP_CTRL) */ | ||
80 | enum { | ||
81 | PMU_AP_CTRL_ID_GRAPHICS = 0x0, | ||
82 | /* PMU_AP_CTRL_ID_MS ,*/ | ||
83 | PMU_AP_CTRL_ID_MAX , | ||
84 | }; | ||
85 | |||
86 | /* AP_CTRL Statistics */ | ||
87 | struct pmu_ap_ctrl_stat { | ||
88 | /* | ||
89 | * Represents whether AP is active or not | ||
90 | * TODO: This is NvBool in RM; is that 1 byte of 4 bytes? | ||
91 | */ | ||
92 | u8 b_active; | ||
93 | |||
94 | /* Idle filter represented by histogram bin index */ | ||
95 | u8 idle_filter_x; | ||
96 | u8 rsvd[2]; | ||
97 | |||
98 | /* Total predicted power saving cycles. */ | ||
99 | s32 power_saving_h_cycles; | ||
100 | |||
101 | /* Counts how many times AP gave us -ve power benefits. */ | ||
102 | u32 bad_decision_count; | ||
103 | |||
104 | /* | ||
105 | * Number of times ap structure needs to skip AP iterations | ||
106 | * KICK_CTRL from kernel updates this parameter. | ||
107 | */ | ||
108 | u32 skip_count; | ||
109 | u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; | ||
110 | }; | ||
111 | |||
112 | /* Parameters initialized by INITn APCTRL command */ | ||
113 | struct pmu_ap_ctrl_init_params { | ||
114 | /* Minimum idle filter value in Us */ | ||
115 | u32 min_idle_filter_us; | ||
116 | |||
117 | /* | ||
118 | * Minimum Targeted Saving in Us. AP will update idle thresholds only | ||
119 | * if power saving achieved by updating idle thresholds is greater than | ||
120 | * Minimum targeted saving. | ||
121 | */ | ||
122 | u32 min_target_saving_us; | ||
123 | |||
124 | /* Minimum targeted residency of power feature in Us */ | ||
125 | u32 power_break_even_us; | ||
126 | |||
127 | /* | ||
128 | * Maximum number of allowed power feature cycles per sample. | ||
129 | * | ||
130 | * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP | ||
131 | * AKA pgPerSampleMax in original algorithm. | ||
132 | */ | ||
133 | u32 cycles_per_sample_max; | ||
134 | }; | ||
135 | |||
136 | /* AP Commands/Message structures */ | ||
137 | |||
138 | /* | ||
139 | * Structure for Generic AP Commands | ||
140 | */ | ||
141 | struct pmu_ap_cmd_common { | ||
142 | u8 cmd_type; | ||
143 | u16 cmd_id; | ||
144 | }; | ||
145 | |||
146 | /* | ||
147 | * Structure for INIT AP command | ||
148 | */ | ||
149 | struct pmu_ap_cmd_init { | ||
150 | u8 cmd_type; | ||
151 | u16 cmd_id; | ||
152 | u8 rsvd; | ||
153 | u32 pg_sampling_period_us; | ||
154 | }; | ||
155 | |||
156 | /* | ||
157 | * Structure for Enable/Disable ApCtrl Commands | ||
158 | */ | ||
159 | struct pmu_ap_cmd_enable_ctrl { | ||
160 | u8 cmd_type; | ||
161 | u16 cmd_id; | ||
162 | |||
163 | u8 ctrl_id; | ||
164 | }; | ||
165 | |||
166 | struct pmu_ap_cmd_disable_ctrl { | ||
167 | u8 cmd_type; | ||
168 | u16 cmd_id; | ||
169 | |||
170 | u8 ctrl_id; | ||
171 | }; | ||
172 | |||
173 | /* | ||
174 | * Structure for INIT command | ||
175 | */ | ||
176 | struct pmu_ap_cmd_init_ctrl { | ||
177 | u8 cmd_type; | ||
178 | u16 cmd_id; | ||
179 | u8 ctrl_id; | ||
180 | struct pmu_ap_ctrl_init_params params; | ||
181 | }; | ||
182 | |||
183 | struct pmu_ap_cmd_init_and_enable_ctrl { | ||
184 | u8 cmd_type; | ||
185 | u16 cmd_id; | ||
186 | u8 ctrl_id; | ||
187 | struct pmu_ap_ctrl_init_params params; | ||
188 | }; | ||
189 | |||
190 | /* | ||
191 | * Structure for KICK_CTRL command | ||
192 | */ | ||
193 | struct pmu_ap_cmd_kick_ctrl { | ||
194 | u8 cmd_type; | ||
195 | u16 cmd_id; | ||
196 | u8 ctrl_id; | ||
197 | |||
198 | u32 skip_count; | ||
199 | }; | ||
200 | |||
201 | /* | ||
202 | * Structure for PARAM command | ||
203 | */ | ||
204 | struct pmu_ap_cmd_param { | ||
205 | u8 cmd_type; | ||
206 | u16 cmd_id; | ||
207 | u8 ctrl_id; | ||
208 | |||
209 | u32 data; | ||
210 | }; | ||
211 | |||
212 | /* | ||
213 | * Defines for AP commands | ||
214 | */ | ||
215 | enum { | ||
216 | PMU_AP_CMD_ID_INIT = 0x0 , | ||
217 | PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, | ||
218 | PMU_AP_CMD_ID_ENABLE_CTRL , | ||
219 | PMU_AP_CMD_ID_DISABLE_CTRL , | ||
220 | PMU_AP_CMD_ID_KICK_CTRL , | ||
221 | }; | ||
222 | |||
223 | /* | ||
224 | * AP Command | ||
225 | */ | ||
226 | union pmu_ap_cmd { | ||
227 | u8 cmd_type; | ||
228 | struct pmu_ap_cmd_common cmn; | ||
229 | struct pmu_ap_cmd_init init; | ||
230 | struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; | ||
231 | struct pmu_ap_cmd_enable_ctrl enable_ctrl; | ||
232 | struct pmu_ap_cmd_disable_ctrl disable_ctrl; | ||
233 | struct pmu_ap_cmd_kick_ctrl kick_ctrl; | ||
234 | }; | ||
235 | |||
236 | /* | ||
237 | * Structure for generic AP Message | ||
238 | */ | ||
239 | struct pmu_ap_msg_common { | ||
240 | u8 msg_type; | ||
241 | u16 msg_id; | ||
242 | }; | ||
243 | |||
244 | /* | ||
245 | * Structure for INIT_ACK Message | ||
246 | */ | ||
247 | struct pmu_ap_msg_init_ack { | ||
248 | u8 msg_type; | ||
249 | u16 msg_id; | ||
250 | u8 ctrl_id; | ||
251 | u32 stats_dmem_offset; | ||
252 | }; | ||
253 | |||
254 | /* | ||
255 | * Defines for AP messages | ||
256 | */ | ||
257 | enum { | ||
258 | PMU_AP_MSG_ID_INIT_ACK = 0x0, | ||
259 | }; | ||
260 | |||
261 | /* | ||
262 | * AP Message | ||
263 | */ | ||
264 | union pmu_ap_msg { | ||
265 | u8 msg_type; | ||
266 | struct pmu_ap_msg_common cmn; | ||
267 | struct pmu_ap_msg_init_ack init_ack; | ||
268 | }; | ||
269 | |||
270 | /* Default Sampling Period of AELPG */ | ||
271 | #define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000) | ||
272 | |||
273 | /* Default values of APCTRL parameters */ | ||
274 | #define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100) | ||
275 | #define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000) | ||
276 | #define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000) | ||
277 | #define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200) | ||
278 | |||
279 | /* | ||
280 | * Disable reason for Adaptive Power Controller | ||
281 | */ | ||
282 | enum { | ||
283 | APCTRL_DISABLE_REASON_RM_UNLOAD, | ||
284 | APCTRL_DISABLE_REASON_RMCTRL, | ||
285 | }; | ||
286 | |||
287 | /* | ||
288 | * Adaptive Power Controller | ||
289 | */ | ||
290 | struct ap_ctrl { | ||
291 | u32 stats_dmem_offset; | ||
292 | u32 disable_reason_mask; | ||
293 | struct pmu_ap_ctrl_stat stat_cache; | ||
294 | u8 b_ready; | ||
295 | }; | ||
296 | |||
297 | /* | ||
298 | * Adaptive Power structure | ||
299 | * | ||
300 | * ap structure provides generic infrastructure to make any power feature | ||
301 | * adaptive. | ||
302 | */ | ||
303 | struct pmu_ap { | ||
304 | u32 supported_mask; | ||
305 | struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; | ||
306 | }; | ||
307 | |||
308 | enum { | 56 | enum { |
309 | GK20A_PMU_DMAIDX_UCODE = 0, | 57 | GK20A_PMU_DMAIDX_UCODE = 0, |
310 | GK20A_PMU_DMAIDX_VIRT = 1, | 58 | GK20A_PMU_DMAIDX_VIRT = 1, |
@@ -316,88 +64,6 @@ enum { | |||
316 | GK20A_PMU_DMAIDX_END = 7 | 64 | GK20A_PMU_DMAIDX_END = 7 |
317 | }; | 65 | }; |
318 | 66 | ||
319 | struct falc_u64 { | ||
320 | u32 lo; | ||
321 | u32 hi; | ||
322 | }; | ||
323 | |||
324 | struct falc_dma_addr { | ||
325 | u32 dma_base; | ||
326 | /*dma_base1 is 9-bit MSB for FB Base | ||
327 | *address for the transfer in FB after | ||
328 | *address using 49b FB address*/ | ||
329 | u16 dma_base1; | ||
330 | u8 dma_offset; | ||
331 | }; | ||
332 | |||
333 | struct pmu_mem_v0 { | ||
334 | u32 dma_base; | ||
335 | u8 dma_offset; | ||
336 | u8 dma_idx; | ||
337 | }; | ||
338 | |||
339 | struct pmu_mem_v1 { | ||
340 | u32 dma_base; | ||
341 | u8 dma_offset; | ||
342 | u8 dma_idx; | ||
343 | u16 fb_size; | ||
344 | }; | ||
345 | |||
346 | struct pmu_mem_v2 { | ||
347 | struct falc_dma_addr dma_addr; | ||
348 | u8 dma_idx; | ||
349 | u16 fb_size; | ||
350 | }; | ||
351 | |||
352 | struct pmu_mem_desc_v0 { | ||
353 | /*! | ||
354 | * Start address of memory surface that is being communicated to the falcon. | ||
355 | */ | ||
356 | struct falc_u64 dma_addr; | ||
357 | /*! | ||
358 | * Max allowed DMA transfer size (size of the memory surface). Accesses past | ||
359 | * this point may result in page faults and/or memory corruptions. | ||
360 | */ | ||
361 | u16 dma_sizemax; | ||
362 | /*! | ||
363 | * DMA channel index to be used when accessing this surface. | ||
364 | */ | ||
365 | u8 dma_idx; | ||
366 | }; | ||
367 | |||
368 | struct pmu_dmem { | ||
369 | u16 size; | ||
370 | u32 offset; | ||
371 | }; | ||
372 | |||
373 | /* Make sure size of this structure is a multiple of 4 bytes */ | ||
374 | struct pmu_cmdline_args_v0 { | ||
375 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
376 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
377 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
378 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
379 | struct pmu_mem_v0 gc6_ctx; /* dmem offset of gc6 context */ | ||
380 | }; | ||
381 | |||
382 | struct pmu_cmdline_args_v1 { | ||
383 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
384 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
385 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
386 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
387 | u8 secure_mode; | ||
388 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | ||
389 | }; | ||
390 | |||
391 | struct flcn_u64 { | ||
392 | u32 lo; | ||
393 | u32 hi; | ||
394 | }; | ||
395 | |||
396 | struct flcn_mem_desc_v0 { | ||
397 | struct flcn_u64 address; | ||
398 | u32 params; | ||
399 | }; | ||
400 | |||
401 | struct pmu_cmdline_args_v2 { | 67 | struct pmu_cmdline_args_v2 { |
402 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | 68 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ |
403 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | 69 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ |
@@ -528,47 +194,11 @@ struct pmu_ucode_desc_v1 { | |||
528 | #define PMU_CMD_FLAGS_EVENT BIT(2) | 194 | #define PMU_CMD_FLAGS_EVENT BIT(2) |
529 | #define PMU_CMD_FLAGS_WATERMARK BIT(3) | 195 | #define PMU_CMD_FLAGS_WATERMARK BIT(3) |
530 | 196 | ||
531 | struct pmu_hdr { | ||
532 | u8 unit_id; | ||
533 | u8 size; | ||
534 | u8 ctrl_flags; | ||
535 | u8 seq_id; | ||
536 | }; | ||
537 | #define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) | 197 | #define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) |
538 | #define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) | 198 | #define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) |
539 | 199 | ||
540 | #define PMU_QUEUE_COUNT 5 | 200 | #define PMU_QUEUE_COUNT 5 |
541 | 201 | ||
542 | struct pmu_allocation_v0 { | ||
543 | u8 pad[3]; | ||
544 | u8 fb_mem_use; | ||
545 | struct { | ||
546 | struct pmu_dmem dmem; | ||
547 | struct pmu_mem_v0 fb; | ||
548 | } alloc; | ||
549 | }; | ||
550 | |||
551 | struct pmu_allocation_v1 { | ||
552 | struct { | ||
553 | struct pmu_dmem dmem; | ||
554 | struct pmu_mem_v1 fb; | ||
555 | } alloc; | ||
556 | }; | ||
557 | |||
558 | struct pmu_allocation_v2 { | ||
559 | struct { | ||
560 | struct pmu_dmem dmem; | ||
561 | struct pmu_mem_desc_v0 fb; | ||
562 | } alloc; | ||
563 | }; | ||
564 | |||
565 | struct pmu_allocation_v3 { | ||
566 | struct { | ||
567 | struct pmu_dmem dmem; | ||
568 | struct flcn_mem_desc_v0 fb; | ||
569 | } alloc; | ||
570 | }; | ||
571 | |||
572 | enum { | 202 | enum { |
573 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | 203 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, |
574 | }; | 204 | }; |
@@ -652,56 +282,6 @@ struct pmu_init_msg { | |||
652 | }; | 282 | }; |
653 | 283 | ||
654 | enum { | 284 | enum { |
655 | PMU_PG_ELPG_MSG_INIT_ACK, | ||
656 | PMU_PG_ELPG_MSG_DISALLOW_ACK, | ||
657 | PMU_PG_ELPG_MSG_ALLOW_ACK, | ||
658 | PMU_PG_ELPG_MSG_FREEZE_ACK, | ||
659 | PMU_PG_ELPG_MSG_FREEZE_ABORT, | ||
660 | PMU_PG_ELPG_MSG_UNFREEZE_ACK, | ||
661 | }; | ||
662 | |||
663 | struct pmu_pg_msg_elpg_msg { | ||
664 | u8 msg_type; | ||
665 | u8 engine_id; | ||
666 | u16 msg; | ||
667 | }; | ||
668 | |||
669 | enum { | ||
670 | PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, | ||
671 | }; | ||
672 | |||
673 | struct pmu_pg_msg_stat { | ||
674 | u8 msg_type; | ||
675 | u8 engine_id; | ||
676 | u16 sub_msg_id; | ||
677 | u32 data; | ||
678 | }; | ||
679 | |||
680 | enum { | ||
681 | PMU_PG_MSG_ENG_BUF_LOADED, | ||
682 | PMU_PG_MSG_ENG_BUF_UNLOADED, | ||
683 | PMU_PG_MSG_ENG_BUF_FAILED, | ||
684 | }; | ||
685 | |||
686 | struct pmu_pg_msg_eng_buf_stat { | ||
687 | u8 msg_type; | ||
688 | u8 engine_id; | ||
689 | u8 buf_idx; | ||
690 | u8 status; | ||
691 | }; | ||
692 | |||
693 | struct pmu_pg_msg { | ||
694 | union { | ||
695 | u8 msg_type; | ||
696 | struct pmu_pg_msg_elpg_msg elpg_msg; | ||
697 | struct pmu_pg_msg_stat stat; | ||
698 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; | ||
699 | /* TBD: other pg messages */ | ||
700 | union pmu_ap_msg ap_msg; | ||
701 | }; | ||
702 | }; | ||
703 | |||
704 | enum { | ||
705 | PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, | 285 | PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, |
706 | }; | 286 | }; |
707 | 287 | ||
@@ -738,175 +318,6 @@ enum { | |||
738 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE | 318 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE |
739 | }; | 319 | }; |
740 | 320 | ||
741 | enum { | ||
742 | PMU_PG_ELPG_CMD_INIT, | ||
743 | PMU_PG_ELPG_CMD_DISALLOW, | ||
744 | PMU_PG_ELPG_CMD_ALLOW, | ||
745 | PMU_PG_ELPG_CMD_FREEZE, | ||
746 | PMU_PG_ELPG_CMD_UNFREEZE, | ||
747 | }; | ||
748 | |||
749 | struct pmu_pg_cmd_elpg_cmd { | ||
750 | u8 cmd_type; | ||
751 | u8 engine_id; | ||
752 | u16 cmd; | ||
753 | }; | ||
754 | |||
755 | struct pmu_pg_cmd_eng_buf_load_v0 { | ||
756 | u8 cmd_type; | ||
757 | u8 engine_id; | ||
758 | u8 buf_idx; | ||
759 | u8 pad; | ||
760 | u16 buf_size; | ||
761 | u32 dma_base; | ||
762 | u8 dma_offset; | ||
763 | u8 dma_idx; | ||
764 | }; | ||
765 | |||
766 | struct pmu_pg_cmd_eng_buf_load_v1 { | ||
767 | u8 cmd_type; | ||
768 | u8 engine_id; | ||
769 | u8 buf_idx; | ||
770 | u8 pad; | ||
771 | struct flcn_mem_desc { | ||
772 | struct falc_u64 dma_addr; | ||
773 | u16 dma_size; | ||
774 | u8 dma_idx; | ||
775 | } dma_desc; | ||
776 | }; | ||
777 | |||
778 | struct pmu_pg_cmd_eng_buf_load_v2 { | ||
779 | u8 cmd_type; | ||
780 | u8 engine_id; | ||
781 | u8 buf_idx; | ||
782 | u8 pad; | ||
783 | struct flcn_mem_desc_v0 dma_desc; | ||
784 | }; | ||
785 | |||
786 | enum { | ||
787 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | ||
788 | }; | ||
789 | |||
790 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 | ||
791 | |||
792 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | ||
793 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | ||
794 | |||
795 | struct pmu_pg_cmd_gr_init_param { | ||
796 | u8 cmd_type; | ||
797 | u16 sub_cmd_id; | ||
798 | u8 featuremask; | ||
799 | }; | ||
800 | |||
801 | struct pmu_pg_cmd_stat { | ||
802 | u8 cmd_type; | ||
803 | u8 engine_id; | ||
804 | u16 sub_cmd_id; | ||
805 | u32 data; | ||
806 | }; | ||
807 | |||
808 | struct pmu_pg_cmd { | ||
809 | union { | ||
810 | u8 cmd_type; | ||
811 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | ||
812 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; | ||
813 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | ||
814 | struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; | ||
815 | struct pmu_pg_cmd_stat stat; | ||
816 | struct pmu_pg_cmd_gr_init_param gr_init_param; | ||
817 | /* TBD: other pg commands */ | ||
818 | union pmu_ap_cmd ap_cmd; | ||
819 | }; | ||
820 | }; | ||
821 | |||
822 | /* ACR Commands/Message structures */ | ||
823 | |||
824 | enum { | ||
825 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 , | ||
826 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, | ||
827 | PMU_ACR_CMD_ID_RESERVED, | ||
828 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, | ||
829 | }; | ||
830 | |||
831 | /* | ||
832 | * Initializes the WPR region details | ||
833 | */ | ||
834 | struct pmu_acr_cmd_init_wpr_details { | ||
835 | u8 cmd_type; | ||
836 | u32 regionid; | ||
837 | u32 wproffset; | ||
838 | |||
839 | }; | ||
840 | |||
841 | /* | ||
842 | * falcon ID to bootstrap | ||
843 | */ | ||
844 | struct pmu_acr_cmd_bootstrap_falcon { | ||
845 | u8 cmd_type; | ||
846 | u32 flags; | ||
847 | u32 falconid; | ||
848 | }; | ||
849 | |||
850 | /* | ||
851 | * falcon ID to bootstrap | ||
852 | */ | ||
853 | struct pmu_acr_cmd_bootstrap_multiple_falcons { | ||
854 | u8 cmd_type; | ||
855 | u32 flags; | ||
856 | u32 falconidmask; | ||
857 | u32 usevamask; | ||
858 | struct falc_u64 wprvirtualbase; | ||
859 | }; | ||
860 | |||
861 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 | ||
862 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 | ||
863 | |||
864 | |||
865 | struct pmu_acr_cmd { | ||
866 | union { | ||
867 | u8 cmd_type; | ||
868 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; | ||
869 | struct pmu_acr_cmd_init_wpr_details init_wpr; | ||
870 | struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; | ||
871 | }; | ||
872 | }; | ||
873 | |||
874 | /* acr messages */ | ||
875 | |||
876 | /* | ||
877 | * returns the WPR region init information | ||
878 | */ | ||
879 | #define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 | ||
880 | |||
881 | /* | ||
882 | * Returns the Bootstrapped falcon ID to RM | ||
883 | */ | ||
884 | #define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 | ||
885 | |||
886 | /* | ||
887 | * Returns the WPR init status | ||
888 | */ | ||
889 | #define PMU_ACR_SUCCESS 0 | ||
890 | #define PMU_ACR_ERROR 1 | ||
891 | |||
892 | /* | ||
893 | * PMU notifies about bootstrap status of falcon | ||
894 | */ | ||
895 | struct pmu_acr_msg_bootstrap_falcon { | ||
896 | u8 msg_type; | ||
897 | union { | ||
898 | u32 errorcode; | ||
899 | u32 falconid; | ||
900 | }; | ||
901 | }; | ||
902 | |||
903 | struct pmu_acr_msg { | ||
904 | union { | ||
905 | u8 msg_type; | ||
906 | struct pmu_acr_msg_bootstrap_falcon acrmsg; | ||
907 | }; | ||
908 | }; | ||
909 | |||
910 | /***************************** ACR ERROR CODES ******************************/ | 321 | /***************************** ACR ERROR CODES ******************************/ |
911 | /*! | 322 | /*! |
912 | * Error codes used in PMU-ACR Task | 323 | * Error codes used in PMU-ACR Task |
@@ -922,47 +333,6 @@ struct pmu_acr_msg { | |||
922 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | 333 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 |
923 | #define PMU_DOMAIN_GROUP_NUM 2 | 334 | #define PMU_DOMAIN_GROUP_NUM 2 |
924 | 335 | ||
925 | /* FECS mem override command*/ | ||
926 | |||
927 | #define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 | ||
928 | |||
929 | /*! | ||
930 | * Enable/Disable FECS error feature | ||
931 | */ | ||
932 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis { | ||
933 | /*Command type must be first*/ | ||
934 | u8 cmd_type; | ||
935 | /*unit bitmask*/ | ||
936 | u8 en_dis_mask; | ||
937 | }; | ||
938 | |||
939 | struct pmu_lrf_tex_ltc_dram_cmd { | ||
940 | union { | ||
941 | u8 cmd_type; | ||
942 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis; | ||
943 | }; | ||
944 | }; | ||
945 | |||
946 | /* FECS mem override messages*/ | ||
947 | #define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0 | ||
948 | |||
949 | struct pmu_msg_lrf_tex_ltc_dram_en_dis { | ||
950 | /*! | ||
951 | * Must be at start | ||
952 | */ | ||
953 | u8 msg_type; | ||
954 | u8 en_fail_mask; | ||
955 | u8 dis_fail_mask; | ||
956 | u32 pmu_status; | ||
957 | }; | ||
958 | |||
959 | struct pmu_lrf_tex_ltc_dram_msg { | ||
960 | union { | ||
961 | u8 msg_type; | ||
962 | struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis; | ||
963 | }; | ||
964 | }; | ||
965 | |||
966 | /* TBD: smart strategy */ | 336 | /* TBD: smart strategy */ |
967 | #define PMU_PERFMON_PCT_TO_INC 58 | 337 | #define PMU_PERFMON_PCT_TO_INC 58 |
968 | #define PMU_PERFMON_PCT_TO_DEC 23 | 338 | #define PMU_PERFMON_PCT_TO_DEC 23 |
@@ -990,136 +360,6 @@ struct pmu_perfmon_counter_v2 { | |||
990 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | 360 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) |
991 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | 361 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) |
992 | 362 | ||
993 | /* PERFMON CMD */ | ||
994 | enum { | ||
995 | PMU_PERFMON_CMD_ID_START = 0, | ||
996 | PMU_PERFMON_CMD_ID_STOP = 1, | ||
997 | PMU_PERFMON_CMD_ID_INIT = 2 | ||
998 | }; | ||
999 | |||
1000 | struct pmu_perfmon_cmd_start_v3 { | ||
1001 | u8 cmd_type; | ||
1002 | u8 group_id; | ||
1003 | u8 state_id; | ||
1004 | u8 flags; | ||
1005 | struct pmu_allocation_v3 counter_alloc; | ||
1006 | }; | ||
1007 | |||
1008 | struct pmu_perfmon_cmd_start_v2 { | ||
1009 | u8 cmd_type; | ||
1010 | u8 group_id; | ||
1011 | u8 state_id; | ||
1012 | u8 flags; | ||
1013 | struct pmu_allocation_v2 counter_alloc; | ||
1014 | }; | ||
1015 | |||
1016 | struct pmu_perfmon_cmd_start_v1 { | ||
1017 | u8 cmd_type; | ||
1018 | u8 group_id; | ||
1019 | u8 state_id; | ||
1020 | u8 flags; | ||
1021 | struct pmu_allocation_v1 counter_alloc; | ||
1022 | }; | ||
1023 | |||
1024 | struct pmu_perfmon_cmd_start_v0 { | ||
1025 | u8 cmd_type; | ||
1026 | u8 group_id; | ||
1027 | u8 state_id; | ||
1028 | u8 flags; | ||
1029 | struct pmu_allocation_v0 counter_alloc; | ||
1030 | }; | ||
1031 | |||
1032 | struct pmu_perfmon_cmd_stop { | ||
1033 | u8 cmd_type; | ||
1034 | }; | ||
1035 | |||
1036 | struct pmu_perfmon_cmd_init_v3 { | ||
1037 | u8 cmd_type; | ||
1038 | u8 to_decrease_count; | ||
1039 | u8 base_counter_id; | ||
1040 | u32 sample_period_us; | ||
1041 | struct pmu_allocation_v3 counter_alloc; | ||
1042 | u8 num_counters; | ||
1043 | u8 samples_in_moving_avg; | ||
1044 | u16 sample_buffer; | ||
1045 | }; | ||
1046 | |||
1047 | struct pmu_perfmon_cmd_init_v2 { | ||
1048 | u8 cmd_type; | ||
1049 | u8 to_decrease_count; | ||
1050 | u8 base_counter_id; | ||
1051 | u32 sample_period_us; | ||
1052 | struct pmu_allocation_v2 counter_alloc; | ||
1053 | u8 num_counters; | ||
1054 | u8 samples_in_moving_avg; | ||
1055 | u16 sample_buffer; | ||
1056 | }; | ||
1057 | |||
1058 | struct pmu_perfmon_cmd_init_v1 { | ||
1059 | u8 cmd_type; | ||
1060 | u8 to_decrease_count; | ||
1061 | u8 base_counter_id; | ||
1062 | u32 sample_period_us; | ||
1063 | struct pmu_allocation_v1 counter_alloc; | ||
1064 | u8 num_counters; | ||
1065 | u8 samples_in_moving_avg; | ||
1066 | u16 sample_buffer; | ||
1067 | }; | ||
1068 | |||
1069 | struct pmu_perfmon_cmd_init_v0 { | ||
1070 | u8 cmd_type; | ||
1071 | u8 to_decrease_count; | ||
1072 | u8 base_counter_id; | ||
1073 | u32 sample_period_us; | ||
1074 | struct pmu_allocation_v0 counter_alloc; | ||
1075 | u8 num_counters; | ||
1076 | u8 samples_in_moving_avg; | ||
1077 | u16 sample_buffer; | ||
1078 | }; | ||
1079 | |||
1080 | struct pmu_perfmon_cmd { | ||
1081 | union { | ||
1082 | u8 cmd_type; | ||
1083 | struct pmu_perfmon_cmd_start_v0 start_v0; | ||
1084 | struct pmu_perfmon_cmd_start_v1 start_v1; | ||
1085 | struct pmu_perfmon_cmd_start_v2 start_v2; | ||
1086 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
1087 | struct pmu_perfmon_cmd_stop stop; | ||
1088 | struct pmu_perfmon_cmd_init_v0 init_v0; | ||
1089 | struct pmu_perfmon_cmd_init_v1 init_v1; | ||
1090 | struct pmu_perfmon_cmd_init_v2 init_v2; | ||
1091 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
1092 | }; | ||
1093 | }; | ||
1094 | |||
1095 | struct pmu_zbc_cmd { | ||
1096 | u8 cmd_type; | ||
1097 | u8 pad; | ||
1098 | u16 entry_mask; | ||
1099 | }; | ||
1100 | |||
1101 | /* PERFMON MSG */ | ||
1102 | enum { | ||
1103 | PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, | ||
1104 | PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, | ||
1105 | PMU_PERFMON_MSG_ID_INIT_EVENT = 2, | ||
1106 | PMU_PERFMON_MSG_ID_ACK = 3 | ||
1107 | }; | ||
1108 | |||
1109 | struct pmu_perfmon_msg_generic { | ||
1110 | u8 msg_type; | ||
1111 | u8 state_id; | ||
1112 | u8 group_id; | ||
1113 | u8 data; | ||
1114 | }; | ||
1115 | |||
1116 | struct pmu_perfmon_msg { | ||
1117 | union { | ||
1118 | u8 msg_type; | ||
1119 | struct pmu_perfmon_msg_generic gen; | ||
1120 | }; | ||
1121 | }; | ||
1122 | |||
1123 | 363 | ||
1124 | struct pmu_cmd { | 364 | struct pmu_cmd { |
1125 | struct pmu_hdr hdr; | 365 | struct pmu_hdr hdr; |