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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h27
1 files changed, 9 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 24bc5822..a53329b4 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -57,15 +57,6 @@ struct nvgpu_firmware;
57#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) 57#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
58#define PMU_PGENG_GR_BUFFER_IDX_FECS (2) 58#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)
59 59
60struct pmu_payload {
61 struct {
62 void *buf;
63 u32 offset;
64 u32 size;
65 u32 fb_size;
66 } in, out;
67};
68
69struct pmu_surface { 60struct pmu_surface {
70 struct nvgpu_mem vidmem_desc; 61 struct nvgpu_mem vidmem_desc;
71 struct nvgpu_mem sysmem_desc; 62 struct nvgpu_mem sysmem_desc;
@@ -119,14 +110,9 @@ struct pmu_pg_stats_data {
119int gk20a_init_pmu_support(struct gk20a *g); 110int gk20a_init_pmu_support(struct gk20a *g);
120int gk20a_init_pmu_bind_fecs(struct gk20a *g); 111int gk20a_init_pmu_bind_fecs(struct gk20a *g);
121 112
113bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
122void gk20a_pmu_isr(struct gk20a *g); 114void gk20a_pmu_isr(struct gk20a *g);
123 115
124/* send a cmd to pmu */
125int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, struct pmu_msg *msg,
126 struct pmu_payload *payload, u32 queue_id,
127 pmu_callback callback, void* cb_param,
128 u32 *seq_desc, unsigned long timeout);
129
130int gk20a_pmu_enable_elpg(struct gk20a *g); 116int gk20a_pmu_enable_elpg(struct gk20a *g);
131int gk20a_pmu_disable_elpg(struct gk20a *g); 117int gk20a_pmu_disable_elpg(struct gk20a *g);
132int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg); 118int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg);
@@ -138,8 +124,14 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
138 124
139int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable); 125int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable);
140 126
141int pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token); 127int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
142int pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token); 128int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
129
130int gk20a_pmu_queue_head(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
131 u32 *head, bool set);
132int gk20a_pmu_queue_tail(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
133 u32 *tail, bool set);
134
143int gk20a_pmu_destroy(struct gk20a *g); 135int gk20a_pmu_destroy(struct gk20a *g);
144int gk20a_pmu_load_norm(struct gk20a *g, u32 *load); 136int gk20a_pmu_load_norm(struct gk20a *g, u32 *load);
145int gk20a_pmu_load_update(struct gk20a *g); 137int gk20a_pmu_load_update(struct gk20a *g);
@@ -157,7 +149,6 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu);
157int gk20a_init_pmu(struct nvgpu_pmu *pmu); 149int gk20a_init_pmu(struct nvgpu_pmu *pmu);
158void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); 150void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
159void gk20a_remove_pmu_support(struct nvgpu_pmu *pmu); 151void gk20a_remove_pmu_support(struct nvgpu_pmu *pmu);
160void pmu_seq_init(struct nvgpu_pmu *pmu);
161 152
162int gk20a_init_pmu(struct nvgpu_pmu *pmu); 153int gk20a_init_pmu(struct nvgpu_pmu *pmu);
163 154